74AC00SC_Q Fairchild Semiconductor, 74AC00SC_Q Datasheet

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74AC00SC_Q

Manufacturer Part Number
74AC00SC_Q
Description
Logic Gates Qd 2-Input NAND Gate
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74AC00SC_Q

Product
NAND
Logic Family
74AC
Number Of Gates
4
Number Of Lines (input / Output)
2 / 1
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Propagation Delay Time
9.5 ns, 8 ns
Supply Voltage - Max
6 V
Supply Voltage - Min
2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-14
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Number Of Output Lines
1
© 1999 Fairchild Semiconductor Corporation
74AC00 • 74ACT00
Quad 2-Input NAND Gate
General Description
The AC/ACT00 contains four 2-input NAND gates.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form. (PC not available in Tape and Reel.)
Logic Symbol
Pin Descriptions
FACT
Order Number
74AC00SC
74AC00SJ
74AC00MTC
74AC00PC
74ACT00SC
74ACT00SJ
74ACT00MTC
74ACT00PC
is a trademark of Fairchild Semiconductor Corporation.
Package Number
MTC14
MTC14
IEEE/IEC
M14A
M14D
M14A
M14D
N14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Small Outline Package (SOP), EIAJ Type II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Small Outline Package (SOP), EIAJ Type II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
A
O
Pin Names
n
n
DS009911
, B
n
Inputs
Outputs
Features
Connection Diagram
Description
I
Outputs source/sink 24 mA
ACT00 has TTL-compatible inputs
CC
reduced by 50%
Package Description
November 1988
Revised November 1999
www.fairchildsemi.com

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74AC00SC_Q Summary of contents

Page 1

... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form. (PC not available in Tape and Reel.) Logic Symbol IEEE/IEC Pin Descriptions FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation Features I reduced by 50% CC ...

Page 2

Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...

Page 3

DC Electrical Characteristics for ACT V CC Symbol Parameter (V) V Minimum HIGH Level 4.5 IH Input Voltage 5.5 V Maximum LOW Level 4.5 IL Input Voltage 5.5 V Minimum HIGH Level 4.5 OH Output Voltage 5.5 4.5 5.5 V ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body www.fairchildsemi.com Package Number M14A 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOIC), EIAJ Type II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide www.fairchildsemi.com Package Number MTC14 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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