74AC02MTC_Q Fairchild Semiconductor, 74AC02MTC_Q Datasheet

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74AC02MTC_Q

Manufacturer Part Number
74AC02MTC_Q
Description
Logic Gates Qd 2-Input NAND Gate
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of 74AC02MTC_Q

Product
NOR
Logic Family
74AC
Number Of Gates
4
Number Of Lines (input / Output)
2 / 1
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Propagation Delay Time
7.5 ns, 6.5 ns
Supply Voltage - Max
6 V
Supply Voltage - Min
2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-14
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Number Of Output Lines
1
©1988 Fairchild Semiconductor Corporation
74AC02, 74ACT02 Rev. 1.5.1
74AC02, 74ACT02
Quad 2-Input NOR Gate
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Description
74AC02SC
74AC02SJ
74AC02MTC
74AC02PC
74ACT02SC
74ACT02MTC
A
O
Order Number
I
Outputs source/sink 24mA
ACT02 has TTL-compatible inputs
n
n
CC
, B
All packages are lead free per JEDEC: J-STD-020B standard.
n
reduced by 50% on 74AC02 only
Pin Names
Package
Number
MTC14
MTC14
M14D
M14A
M14A
N14A
Inputs
Outputs
Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
General Description
The AC02/ACT02 contains four, 2-input NOR gates.
Logic Symbol
Package Description
IEEE/IEC
January 2008
www.fairchildsemi.com

Related parts for 74AC02MTC_Q

74AC02MTC_Q Summary of contents

Page 1

... B Inputs Outputs n ©1988 Fairchild Semiconductor Corporation 74AC02, 74ACT02 Rev. 1.5.1 General Description The AC02/ACT02 contains four, 2-input NOR gates. Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4 ...

Page 2

... V Output Voltage O T Operating Temperature Minimum Input Edge Rate, AC Devices: V from 30 Minimum Input Edge Rate, ACT Devices: V from 0.8V to 2.0V ©1988 Fairchild Semiconductor Corporation 74AC02, 74ACT02 Rev. 1.5.1 Parameter Parameter , V @ 3.3V, 4.5V, 5. 4.5V, 5. Rating –0.5V to +7.0V –20mA +20mA –0. 0.5V CC – ...

Page 3

... All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5. ©1988 Fairchild Semiconductor Corporation 74AC02, 74ACT02 Rev. 1.5.1 T +25° ...

Page 4

... OLD (5) Output Current I OHD I Maximum Quiescent CC Supply Current Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC02, 74ACT02 Rev. 1.5.1 T +25° (V) Conditions Typ. 4.5 V ...

Page 5

... AC Electrical Characteristics for ACT Symbol Parameter t Propagation Delay PLH t Propagation Delay PHL Note: 7. Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter C Input Capacitance IN C Power Dissipation Capacitance PD ©1988 Fairchild Semiconductor Corporation 74AC02, 74ACT02 Rev. 1.5.1 T +25° 50pF L (6) V (V) Min. Typ. Max. CC 3.3 1.5 5.0 7.5 5.0 1 ...

Page 6

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 7

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 8

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 9

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 10

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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