CD4011BCN_Q Fairchild Semiconductor, CD4011BCN_Q Datasheet
CD4011BCN_Q
Specifications of CD4011BCN_Q
Related parts for CD4011BCN_Q
CD4011BCN_Q Summary of contents
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... Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP, SOIC and SOP CD4001BC Top View © 1999 Fairchild Semiconductor Corporation Features Low power TTL: Fan out of 2 driving 74L compatibility driving 74LS 5V–10V–15V parametric ratings ...
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Schematic Diagrams www.fairchildsemi.com CD4001BC device shown Logical “1” HIGH Logical “0” LOW All inputs protected by standard CMOS protection circuit. CD4011BC device shown • B Logical “1” ...
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Absolute Maximum Ratings (Note 2) Voltage at any Pin 0. Power Dissipation ( Dual-In-Line Small Outline V Range 0 Storage Temperature ( Lead Temperature ( (Soldering, 10 seconds) DC Electrical ...
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AC Electrical Characteristics CD4011BC Input ns pF Symbol Parameter t Propagation Delay, PHL HIGH-to-LOW Level t Propagation Delay, PLH LOW-to-HIGH Level Transition Time ...
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Typical Transfer Characteristics 5 www.fairchildsemi.com ...
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www.fairchildsemi.com 6 ...
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Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14A Package Number M14D 7 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN ...