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BR93L46FV-WE2
BR93L46FV-WE2 | |
|---|---|
| Manufacturer Part Number | BR93L46FV-WE2 |
| Description | IC EEPROM 1KBIT 2MHZ 8SSOP |
| Manufacturer | Rohm Semiconductor |
| BR93L46FV-WE2 datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
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Specifications of BR93L46FV-WE2 | |||
|---|---|---|---|
| Format - Memory | EEPROMs - Serial | Memory Type | EEPROM |
| Memory Size | 1K (64 x 16) | Speed | 2MHz |
| Interface | Microwire, 3-Wire Serial | Voltage - Supply | 1.8 V ~ 5.5 V |
| Operating Temperature | -40°C ~ 85°C | Package / Case | 8-SSOP |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | Other names | BR93L46FV-WE2 BR93L46FV-WE2TR |
PrevNext
BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series
●Application
1) Method to cancel each command
○READ
Start bit
Ope code
1bit
2bit
Cancel is available in all areas in read mode.
・Method to cancel：cancel by CS=“L”
Fig.66 READ cancel available timing
○WRITE, WRAL
Start bit
Ope code
1bit
2bit
2
a：From start bit to 25 clock rise
＊
Cancel by CS=“L”
2
＊
b：25 clock rise and after
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
And when SK clock is input continuously, cancellation is not available.
Start bit
Ope code
1bit
2bit
a：From start bit to 29 clock rise
Cancel by CS=“L”
b：29 clock rise and after
Cancellation is not available by any means. If Vcc is made OFF in this area,
designated address data is not guaranteed, therefore write once again.
c：30 clock rise and after
Cancel by CS=“L”
However, when write is started in b area (CS is ended), cancellation is not
available by any means.
And when SK clock is output continuously is not available.
Fig.67 WRITE, WRAL cancel available timing
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
*1
(In the case of BR93L46-W/A46-WM)
Address
Data
6bit
16bit
＊1 Address is 8 bits in BR93L56-W/A56-WM, BR93L-66W/A66-WM
Address is 10 bits in BR93L76-W/A76-WM, BR93L86-W/A86-WM
・25 Rise of clock
*2
SK
24
25
DI
D1
D0
Enlarged figure
*1
Address
Data
tE/W
6bit
16bit
a
b
*1 Address is 8 bits in BR93L56-W/A56-WM, BR93L66-W/A66-WM
Address is 10 bits in BR93L76-W/A76-WM BR93L86-W/A86-WM
*2 27 clocks in BR93L56-W/A56-WM, BR93L66-W/A66-WM
29 clocks in BR93L76-W/A76-WM BR93L86-W/A86-WM
29 Rise of clock
*2
SK
28
29
30
31
D1
D0
DI
a
b
c
Enlarged figure
*1
Address
Data
tE/W
10bit
16bit
a
c
b
Note 1) If Vcc is made OFF in this area, designated address data is
Note 2) If CS is started at the same timing as that of the SK rise,
14/40
Technical Note
(In the case of BR93L46-W/A46-WM)
(In the case of BR93L86-W/A86-WM)
not guaranteed, therefore write once again.
write execution/cancel becomes unstable, therefore, it is
recommended to fail in SK=”L” area.
As for SK rise, recommend timing of tCSS/tCSH or higher.
2011.02 - Rev.F
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