71V35761S200PFG

Manufacturer Part Number71V35761S200PFG
DescriptionSRAM 128Kx36 SYNC 3.3V PIPELINED BURST SRAM
ManufacturerIDT
71V35761S200PFG datasheet
 


Specifications of 71V35761S200PFG

RohsyesMemory Size4 Mbit
Organization128 K x 36Access Time3.1 ns
Supply Voltage - Max3.465 VSupply Voltage - Min3.135 V
Maximum Operating Current360 mAMaximum Operating Temperature+ 70 C
Minimum Operating Temperature0 CMounting StyleSMD/SMT
Package / CaseTQFP-100Part # AliasesIDT71V35761S200PFG
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
Page 1/21

Download datasheet (326Kb)Embed
Next
Features
◆ ◆ ◆ ◆ ◆
128K x 36 memory configurations
◆ ◆ ◆ ◆ ◆
Supports high system speed:
Commercial:
– 200MHz 3.1ns clock access time
Commercial and Industrial:
– 183MHz 3.3ns clock access time
– 166MHz 3.5ns clock access time
◆ ◆ ◆ ◆ ◆
LBO input selects interleaved or linear burst mode
◆ ◆ ◆ ◆ ◆
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
◆ ◆ ◆ ◆ ◆
3.3V core power supply
◆ ◆ ◆ ◆ ◆
Power down controlled by ZZ input
◆ ◆ ◆ ◆ ◆
3.3V I/O
◆ ◆ ◆ ◆ ◆
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆ ◆ ◆ ◆ ◆
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
Pin Description Summary
A
-A
Address Inputs
0
17
CE
Chip Enable
, CS
CS
Chip Selects
0
1
OE
Output Enable
GW
Global Write Enable
BWE
Byte Write Enable
BW
, BW
, BW
, BW
(1)
Individual Byte Write Selects
1
2
3
4
CLK
Clock
ADV
Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO
Linear / Interleaved Burst Order
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock
TDO
Test Data Output
TRST
JTAG Reset (Optional)
ZZ
Sleep Mode
I/O
-I/O
, I/O
-I/O
Data Input / Output
0
31
P1
P4
V
, V
Core Power, I/O Power
DD
DDQ
V
Ground
SS
©2010 Integrated Device Technology, Inc.
128K x 36
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
Description
The IDT71V35761 are high-speed SRAMs organized as
128K x 36. The IDT71V35761 SRAMs contain write, data, address and
control registers. Internal logic allows the SRAM to generate a self-timed
write based upon a decision which can be left until the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V35761 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The IDT71V35761 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array.
1
IDT71V35761YS/S
IDT71V35761YSA/SA
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
Asynchronous
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
N/A
Input
Synchronous
Input
Synchronous
Input
Synchronous
Input
DC
Input
Synchronous
Input
Synchronous
Input
N/A
Output
Synchronous
Input
Asynchronous
Input
Asynchronous
I/O
Synchronous
Supply
N/A
Supply
N/A
5301 tbl 01
MAY 2010
DSC-5301/05

71V35761S200PFG Summary of contents

  • Page 1

    ... The burst mode feature offers the highest level of performance to the system designer, as the IDT71V35761 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence ...

  • Page 2

    ... LOW be left floating. This pin has an inte rnal pullup. Only available in BGA package. Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V35761/35781 HIGH to its lowest power consumption level. Data retention is guaranteed in Slee p Mode.This pin has an internal pull down ...

  • Page 3

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Functional Block Diagram Commercial and Industrial Temperature Ranges 6.42 3 ...

  • Page 4

    ... -55 to +125 2.0 W NOTES (max (min) = -1.0V for pulse width less than t 5301 tbl 03 IL during power supply ramp up. 119 BGA Capacitance (T = +25° 1.0MHz) A Max. Unit Symbol = 3dV 3dV 7 pF OUT ...

  • Page 5

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36 100 DDQ DDQ ...

  • Page 6

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36, 119 BGA DDQ I I DDQ I I DDQ DDQ N I DDQ NOTES connected to an input voltage ≥ ...

  • Page 7

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36, 165 fBGA ( I DDQ D I/O I DDQ E I/O I DDQ F I/O I DDQ G I/O I DDQ ...

  • Page 8

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter |I | Input Leakage Current LI ZZ, LBO and JTAG Input Leakage Current |I | LZZ |I | Output Leakage Current LO V Output Low Voltage ...

  • Page 9

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Synchronous Truth Table Operation Address Used Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down ...

  • Page 10

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Synchronous Write Function Truth Table GW Operation Read H Read H Write all Bytes L Write all Bytes H (3) Write Byte 1 H (3) Write Byte 2 H (3) Write Byte 3 H (3) Write Byte 4 H NOTES: 1 ...

  • Page 11

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect AC Electrical Characteristics (V = 3.3V ±5%, Commercial and Industrial Temperature Ranges) DD Symbol Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse Width t CL Output Parameters t Clock High to Valid Data ...

  • Page 12

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Pipelined Read Cycle Commercial and Industrial Temperature Ranges (1,2) , 6.42 12 ...

  • Page 13

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Combined Pipelined Read and Write Cycles Commercial and Industrial Temperature Ranges , 6.42 13 (1,2,3) ...

  • Page 14

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No Controlled Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

  • Page 15

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No Byte Controlled Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

  • Page 16

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Sleep (ZZ) and Power-Down Modes Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

  • Page 17

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Non-Burst Read Cycle Timing Waveform CLK ADSP ADSC ADDRESS GW, BWE, BWx CE DATA OUT NOTES input is LOW, ADV is HIGH and LBO is Don't Care for this cycle. ...

  • Page 18

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect JTAG Interface Specification (SA Version only TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO ( 3) TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. 2. Device outputs = All device outputs except TDO. ...

  • Page 19

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect JTAG Identification Register Definitions (SA Version only) Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) Available JTAG Instructions Instruction EXTEST SAMPLE/PRELOAD DEVICE_ID HIGHZ RESERVED ...

  • Page 20

    ... IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Ordering Information Package Information 100-Pin Thin Quad Plastic Flatpack (TQFP) 119 Ball Grid Array (BGA) 165 Fine Pitch Ball Grid Array (fBGA) Information available on the IDT website Commercial and Industrial Temperature Ranges 6 ...

  • Page 21

    ... CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Created new datasheet from 71v3576 and 71v3578 datasheet. Added industrial temperature range offering from 166MHz and 183MHz Added 100 pin TQFP package Diagram Outline Add BGA capacitance table ...