71V3578S133PFG IDT, 71V3578S133PFG Datasheet

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71V3578S133PFG

Manufacturer Part Number
71V3578S133PFG
Description
SRAM 256Kx18 SYNC 3.3V FLOW-THROUGH SRAM
Manufacturer
IDT
Datasheet

Specifications of 71V3578S133PFG

Rohs
yes
Memory Size
4 Mbit
Organization
128 K x 36
Access Time
4.2 ns
Supply Voltage - Max
3.465 V
Supply Voltage - Min
3.135 V
Maximum Operating Current
250 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TQFP-100
Part # Aliases
IDT71V3578S133PFG
Features
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NOTE:
1. BW
Pin Description Summary
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
©2012 Integrated Device Technology, Inc.
CS
CLK
I/O
A
CE
OE
GW
BWE
BW
ADV
ADSC
ADSP
LBO
ZZ
V
V
0
DD
SS
-A
0
0
128K x 36, 256K x 18 memory configurations
Supports high system speed:
Commercial and Industrial:
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP)
1
-I/O
, CS
, V
, BW
17
DDQ
3
31
1
, I/O
and BW
2
, BW
P1
-I/O
3
, BW
4
P4
are not applicable for the IDT71V3578.
4
(1)
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Linear / Interleaved Burst Order
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Address Inputs
Address Status (Cache Controller)
Address Status (Processor)
128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
1
Description
128K x 36/256K x 18. The IDT71V3576/78 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
system designer, as the IDT71V3576/78 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP).
The IDT71V3576/78 are high-speed SRAMs organized as
The burst mode feature offers the highest level of performance to the
The IDT71V3576/78 SRAMs utilize IDT’s latest high-performance
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
FEBRUARY 2012
IDT71V3576S
IDT71V3578S
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
N/A
N/A
N/A
DC
DSC-5279/06
5279 tbl 01

Related parts for 71V3578S133PFG

71V3578S133PFG Summary of contents

Page 1

... SS NOTE and BW are not applicable for the IDT71V3578 The IDT logo is a registered trademark of Integrated Device Technology, Inc. ©2012 Integrated Device Technology, Inc. 128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect Description The IDT71V3576/78 are high-speed SRAMs organized as 128K x 36/256K x 18 ...

Page 2

... When OE is HIGH the I/O pins are in a high-impedance state. Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the HIGH IDT71V3576/78 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull down. N/A 3 ...

Page 3

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Functional Block Diagram Commercial and Industrial Temperature Ranges 6.42 3 ...

Page 4

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Absolute Maximum Ratings Symbol Rating (2) V Terminal Voltage with TERM Respect to GND (3,6) V Terminal Voltage with TERM Respect to GND (4,6) V Terminal Voltage with TERM Respect to GND (5,6) V Terminal Voltage with -0 ...

Page 5

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 128K x 36 100 DDQ DDQ ...

Page 6

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Pin Configuration – 256K DDQ I I DDQ ...

Page 7

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter |I | Input Leakage Current LI ZZ and LBO Input Leakage Current |I | LZZ |I | Output Leakage Current ...

Page 8

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Synchronous Truth Table Operation Address Used Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down ...

Page 9

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Synchronous Write Function Truth Table GW Operation Read H Read H Write all Bytes L Write all Bytes H (3) Write Byte 1 H (3) Write Byte 2 H (3) Write Byte 3 H (3) Write Byte 4 ...

Page 10

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect AC Electrical Characteristics (V = 3.3V ±5%, Commercial and Industrial Temperature Ranges) DD Symbol Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse Width t CL Output Parameters ...

Page 11

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Pipelined Read Cycle Commercial and Industrial Temperature Ranges (1,2) , 6.42 11 ...

Page 12

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Combined Pipelined Read and Write Cycles Commercial and Industrial Temperature Ranges , 6.42 12 (1,2,3) ...

Page 13

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No Controlled Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

Page 14

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Write Cycle No Byte Controlled Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

Page 15

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Timing Waveform of Sleep (ZZ) and Power-Down Modes Commercial and Industrial Temperature Ranges (1,2,3) 6. ...

Page 16

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Non-Burst Read Cycle Timing Waveform CLK ADSP ADSC ADDRESS GW, BWE, BWx CE DATA OUT NOTES input is LOW, ADV is HIGH and LBO is Don't Care for this cycle. ...

Page 17

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Ordering Information XXX Power Device Speed Package Type Package Information 100-Pin Thin Quad Plastic Flatpack (TQFP) Information available on the IDT website Process/ Temperature ...

Page 18

... IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Datasheet Document History 7/26/99 9/17/99 Pg. 8 Pg. 11 Pg. 18 Pg. 20 12/31/99 Pg 11 11, 19 04/04/00 Pg.18 Pg. 4 Pg. 7 06/01/00 Pg. 20 07/15/00 Pg. 7 Pg. 8 Pg. 20 10/25/00 Pg. 8 04/22/03 Pg. 4 06/30/03 Pg. 1,2,3,5-9 Pg. 5-8 Pg. 19,20 Pg. 21-23 Pg. 24 01/01/04 Pg.21 01/20/10 Pg.1,2,4,7,8 Pg.19,20,21 02/25/12 Pg.1,2,3,7,17 CORPORATE HEADQUARTERS ...

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