71V3578S133PFG IDT, 71V3578S133PFG Datasheet - Page 2

• Manufacturer Part Number: 71V3578S133PFG
• Description: SRAM 256Kx18 SYNC 3.3V FLOW-THROUGH SRAM
• Manufacturer: IDT

Specifications of 71V3578S133PFG

• Rohs: yes
• Memory Size: 4 Mbit
• Organization: 128 K x 36
• Access Time: 4.2 ns
• Supply Voltage - Max: 3.465 V
• Supply Voltage - Min: 3.135 V
• Maximum Operating Current: 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Part # Aliases: IDT71V3578S133PFG

Pin Definitions
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
I/O
BW
I/O
Symbol
A
ADSC
ADSP
BWE
V
ADV
P1
LBO
CLK
CS
CS
GW
V
V
0
CE
OE
0
NC
1
ZZ
DDQ
-A
-I/O
DD
SS
-BW
-I/O
0
1
17
31
P4
4
Linear Burst Order
Byte Write Enable
(Cache Controller)
Data Input/Output
Address Inputs
Address Status
Address Status
Individual Byte
Burst Address
Write Enables
Output Enable
Power Supply
Power Supply
Chip Select 0
Pin Function
Chip Select 1
Sleep Mode
Chip Enable
Global Write
(Processor)
No Connect
Advance
Ground
Enable
Clock
(1)
N/A
N/A
N/A
N/A
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Active
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge
of CLK and ADSC Low or ADSP Low and CE Low.
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load
the address registers with new addresses.
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the
address registers with new addresses. ADSP is gated by CE.
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal
burst counter, controlling burst access after the initial address is loaded. When the input is HIGH the
burst counter is not incremented; that is, there is no address advance.
Synchronous byte write enable gates the byte write inputs BW
edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the
byte write inputs are blocked and only GW can initiate a write cycle.
Synchronous byte write enables. BW
active byte write causes all outputs to be disabled.
Synchronous chip enable. CE is used with CS
ADSP.
This is the clock input. All timing references for the device are made with respect to this input.
Synchronous active HIGH chip select. CS
Synchronous active LOW chip select. CS
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising
edge of CLK. GW supersedes individual byte write enables.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered
and triggered by the rising edge of CLK.
Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is
selected. When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must
not change state while the device is operating.
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if
the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V3576/78 to its lowest power consumption level. Data retention is guaranteed in Sleep
Mode.This pin has an internal pull down.
3.3V core power supply.
3.3V I/O Supply.
Ground.
NC pins are not electrically connected to the device.
6.42
2
1
controls I/O
Commercial and Industrial Temperature Ranges
1
0
is used with CE and CS
is used with CE and CS
0
and CS
0-7
, I/O
1
P1
to enable the IDT71V3576/78. CE also gates
, BW
1
-BW
2
controls I/O
0
4
1
. If BWE is LOW at the rising
to enable the chip.
to enable the chip.
8-15
, I/O
P2
, etc. Any
5279 tbl 02