71V35761S183PFGI IDT, 71V35761S183PFGI Datasheet - Page 2

• Manufacturer Part Number: 71V35761S183PFGI
• Description: SRAM 128Kx36 SYNC 3.3V PIPELINED BURST SRAM
• Manufacturer: IDT

Specifications of 71V35761S183PFGI

• Rohs: yes
• Memory Size: 128 KB
• Organization: 128 K x 36
• Access Time: 3.3 ns
• Supply Voltage - Max: 3.465 V
• Supply Voltage - Min: 3.135 V
• Maximum Operating Current: 350 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Memory Type: Synchronous
• Part # Aliases: IDT71V35761S183PFGI

Pin Definitions
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
IDT71V35761, 128K x 36, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
I/O
BW
I/O
Symbol
A
ADSC
ADSP
TRST
BWE
V
ADV
P1
TMS
LBO
TCK
TDO
CLK
CS
GW
V
V
0
CS
CE
0
OE
TDI
NC
1
ZZ
DDQ
-A
-I/O
DD
SS
-BW
-I/O
0
1
17
31
P4
4
11
Linear Burst Order
(Cache Controller)
Byte Write Enable
Test ModeSelect
Data Input/Output
Test DataOutput
Address Status
Address Status
Address Inputs
Individual Byte
Test Data Input
Burst Address
Write Enables
Output Enable
Power Supply
Power Supply
Pin Function
Chip Select 0
Chip Select 1
Sleep Mode
Chip Enable
Global Write
JTAG Reset
No Connect
(Processor)
Test Clock
(Optional)
Advance
Ground
Enable
Clock
(1)
N/A
N/A
N/A
N/A
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Active
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK
and ADSC Low or ADSP Low and CE Low.
Synchro nous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the
address registers with new addresses.
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address
registers with new addresses. ADSP is gated by CE.
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst
counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is
not incremented; that is, there is no address advance.
Synchronous byte write enable gates the byte write inputs BW
blocked and only GW can initiate a write cycle.
Synchronous byte write enables. BW
Synchronous chip enable. CE is used with CS
Synchrono us active HIGH chip select. CS
Synchronous active LOW chip select. CS
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
CLK. GW supersedes individual byte write enables.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed be tween TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an inte rnal pullup. Only available in BGA package.
pull down.
Ground.
NC pins are not electrically connected to the device.
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are
write causes all outputs to be disabled.
ADSP.
This is the clock input. All timing references for the device are made with respect to this input.
triggered by the rising edge of CLK.
Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is selected.
When LBO is LOW the Line ar burst sequence is selected. LBO is a static input and must not change state
while the device is operating.
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TAP controller.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V35761/35781
to its lowest power consumption level. Data retention is guaranteed in Slee p Mode.This pin has an internal
3.3V core power supply.
3.3V I/O Supply.
6.42
2
1
controls I/O
1
0
is used with CE and CS
is used with CE and CS
0
Commercial and Industrial Temperature Ranges
and CS
Description
0-7
, I/O
1
P1
to enable the IDT71V35761/781. CE also gates
, BW
1
-BW
2
controls I/O
0
1
4
. If BWE is LOW at the rising edge of CLK
to enable the chip.
to enable the chip.
8-15
, I/O
P2
, etc. Any active byte
5301tbl 02