71V124SA15PHG IDT, 71V124SA15PHG Datasheet

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71V124SA15PHG

Manufacturer Part Number
71V124SA15PHG
Description
SRAM 128Kx8 ASYNCHRONOUS 3.3V STATIC RAM
Manufacturer
IDT
Datasheet

Specifications of 71V124SA15PHG

Rohs
yes
Part # Aliases
IDT71V124SA15PHG
Features
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Functional Block Diagram
©
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Equal access and cycle times
– Commercial: 10/12/15ns
– Industrial: 12/15ns
One Chip Select plus one Output Enable pin
Inputs and outputs are LVTTL-compatible
Single 3.3V supply
Low power consumption via chip deselect
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
I/O
0
- I/O
A
A
16
7
0
WE
OE
CS
8
ADDRESS
DECODER
8
3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
CONTROL
LOGIC
1
Description
as 128K x 8. It is fabricated using high-performance, high-reliability CMOS
technology. This state-of-the-art technology, combined with innovative
circuit design techniques, provides a cost-effective solution for high-speed
memory needs. The JEDEC center power/GND pinout reduces noise
generation and improves system performance.
5ns, with address access times as fast as 10ns available. All bidirectional
inputs and outputs of the IDT71V124 are LVTTL-compatible and operation
is from a single 3.3V supply. Fully static asynchronous circuitry is used;
no clocks or refreshes are required for operation.
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
The IDT71V124 has an output enable pin which operates as fast as
MEMORY ARRAY
I/O CONTROL
1,048,576-BIT
3873 drw 01
FEBRUARY 2013
IDT71V124SA
8
.
DSC-3873/11

Related parts for 71V124SA15PHG

71V124SA15PHG Summary of contents

Page 1

... The JEDEC center power/GND pinout reduces noise generation and improves system performance. The IDT71V124 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns available. All bidirectional inputs and outputs of the IDT71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used ...

Page 2

... OUT V IL 3873 tbl 03 NOTES: 1. For 71V124SA10 only. 2. For all speed grades except 71V124SA10 (max (min.) = –2V for pulse width less than 5ns, once per cycle. IL Test Conditions V = Max., V GND Max., GND to V ...

Page 3

... IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout DC Electrical Characteristics (V = Min. to Max 0.2V Symbol I Dynamic Operating Current CC CS < Outputs Open Dynamic Standby Power Supply Current SB CS > Outputs Open Full Standby Power Supply Current (static) SB1 CS > ...

Page 4

... IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout AC Electrical Characteristics (V = Min. to Max., Commercial and Industrial Temperature Ranges) DD Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Select Access Time ACS (1) t Chip Select to Output in Low-Z ...

Page 5

... IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Timing Waveform of Read Cycle No. 1 ADDRESS OE CS HIGH IMPEDANCE DATA OUT Timing Waveform of Read Cycle No. 2 ADDRESS PREVIOUS DATA DATA OUT OUT NOTES HIGH for Read Cycle. 2. Device is continuously selected LOW. ...

Page 6

... IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Timing Waveform of Write Cycle No. 1 (WE Controlled Timing) ADDRESS (3) DATA OUT DATA IN Timing Waveform of Write Cycle No. 2 (CS Controlled Timing) ADDRESS DATA IN NOTES write occurs during the overlap of a LOW CS and a LOW WE. ...

Page 7

... IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Ordering Information 71V124 Device Power Speed Package Type Process/ Temperature Range Blank 8 Blank I Green 6.42 Commercial and Industrial Temperature Ranges Tube or Tray Tape and Reel Commercial (0° ...

Page 8

... Pg. 1,3,4,7 Removed 20ns commercial, 10ns & 20ns industrial and also removed HSA offering 02/01/13: Pg. 1 Removed IDT reference to fabrication and changed fastest access address time from 9ns to 10ns CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. ...

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