71V3558S200PFG IDT, 71V3558S200PFG Datasheet

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71V3558S200PFG

Manufacturer Part Number
71V3558S200PFG
Description
SRAM
Manufacturer
IDT
Datasheet

Specifications of 71V3558S200PFG

Product Category
SRAM
Rohs
yes
Part # Aliases
IDT71V3558S200PFG
Features
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Pin Description Summary
R/W
CLK
I/O
A
CE
OE
CEN
BW
ADV/LD
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
V
V
©
0
DD
SS
-A
2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
0
128K x 36, 256K x 18 memory configurations
Supports high performance system speed - 200 MHz (x18)
(3.2 ns Clock-to-Data Access)
Supports high performance system speed - 166 MHz (x36)
(3.5 ns Clock-to-Data Access)
ZBT
cycles
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
Three chip enables for simple depth expansion
3.3V power supply (±5%), 3.3V I/O Supply (V
Optional- Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
1
1
-I/O
, CE
, V
, BW
17
DDQ
31
2
TM
, I/O
, CE
2
, BW
Feature - No dead cycles between write and read
P1
2
3
-I/O
, BW
P4
4
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Linear / Interleaved Burst Order
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Address Inputs
Advance b urst address / Load new address
Test Mode Select
Test Data Input
Test Clock
Test Data Output
1
- BW
4
) control (May tie active)
128K x 36, 256K x 18
3.3V Synchronous ZBT SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs
DDQ)
1
Description
bit) synchronous SRAMS. They are designed to eliminate dead bus
writes and reads. Thus, they have been given the name ZBT
Zero Bus Turnaround.
registers. Output enable is the only asynchronous signal and can be
used to disable the outputs at any given time.
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
user to deselect the device when desired. If any one of these three are
not asserted when ADV/LD is low, no new memory operation can be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
initiated. However, any pending data transfers (reads or writes) will be
their previous values.
cycles when turning the bus around between reads and writes, or
clock cycle, and two cycles later the associated data cycle occurs, be
it read or write.
The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
The IDT71V3556/58 contain data I/O, address and control signal
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58
There are three chip enable pins (CE
Address and control signals are applied to the SRAM during one
Supply
Supply
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
IDT71V3556SA/XSA
IDT71V3558SA/XSA
IDT71V3556S/XS
IDT71V3558S/XS
1
Asynchronous
Asynchronous
, CE
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
OCTOBER 2010
Static
Static
Static
N/A
N/A
2
, CE
2
) that allow the
DSC-5281/11
5281 tbl 01
TM
, or

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