71V2556S133PFG IDT, 71V2556S133PFG Datasheet - Page 7

• Manufacturer Part Number: 71V2556S133PFG
• Description: SRAM
• Manufacturer: IDT

Specifications of 71V2556S133PFG

• Product Category: SRAM
• Rohs: yes
• Part # Aliases: IDT71V2556S133PFG

Synchronous Truth Table
Partial Truth Table for Writes
NOTES:
1. L = V
2. Multiple bytes may be selected during the same cycle.
NOTES:
1. L = V
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
3. Deselect cycle is initiated when either (CE
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
5. To select the chip requires CE
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
R
N
W
W
W
W
W
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
E
O
C
I R
I R
I R
I R
I R
A
E
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
tri-state two cycles after deselect is initiated.
Os remains unchanged.
H
L
L
L
L
L
L
W
E T
E T
E T
E T
E T
D
N
I R
A
B
B
B
B
E T
IL
IL
L L
Y
Y
Y
Y
, H = V
, H = V
E T
E T
E T
E T
/ R W
B
H
X
X
X
X
X
L
Y
1
2
3
4
E T
I (
I (
I (
I (
IH
IH
O /
O /
O /
O /
, X = Don’t Care.
S
, X = Don’t Care.
0 [
: 8 [
1 [
2 [
e D
E
7 :
: 6
: 4
C
e S
e S
5 1
n
h
e s
I , ]
3 2
1 3
b a
X
X
X
X
p i
e l
e l
I , ]
I , ]
I , ]
e l
O /
) 5 (
t c
t c
e l
O /
t c
1 P
O /
O /
2 P
)
3 P
4 P
O
) 2 (
)
1
) 2 (
P
)
)
) 2 (
) 2 (
= L, CE
A
E
R
D
T A
/ V
H
H
H
X
L
L
L
L
O I
D
2
N
1
= L, CE
, or CE
B x
a V
a V
W
X
X
X
X
X
d i l
d i l
2
2
= H on these chip enables. Chip is deselected if any one of the chip enables is false.
(1)
is sampled high or CE
A
x E
x E
D
n I
n I
U
D
e t
e t
S
(1)
e t
e t
R
X
X
X
E
n r
n r
n r
n r
E
D
l a
l a
S
l a
l a
S
2
6.42
is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
D
P
7
E
R
L
B
L
B
S
E
O
O
U
U
E
/ R W
V
A
A
R
R
E L
H
L
L
L
L
L
L
O I
D
D
S
S
U
T
C
W
T
X
X
X
X
R
S
/ T
W
E
I R
R
A
C
E
I R
E T
N
D
Y
A
E T
O
C
D
/
/
E L
O
P
B
X
W
L
L
H
H
H
H
Commercial and Industrial Temperature Ranges
1
A (
A (
D
v d
v d
E
C
n a
n a
S
U
B
B
L
E
L
R
S
U
e c
e c
O
U
E L
O
R
U
R
B
R
A
A
E
N
S
S
W
X
L
H
L
H
H
H
u b
S
u b
C
D
D
N
O
P
T
T
T
2
T
s r
s r
E
W
O
R
W
r o
R
N
E
c t
c t
P
C
I R
E
I R
D
A
Y
S
E T
A
u o
u o
) 4 (
E T
C
D
T
D
E L
O
t n
t n
P
) r e
) r e
) 3 (
) 2 (
) 2 (
B
W
X
L
H
H
L
H
H
3
2 (
r P
v e
y c
o i
l c
I
O /
Q
Q
D
D
H
H
s u
s e
) 7 (
) 7 (
) 7 (
) 7 (
Z i
Z i
B
) 6 (
W
X
H
H
H
H
L
L
8 4
V
8 4
t a l
l a
5 7
4
5 7
) r e
e u
l b t
l b t
8 0
9 0