7024S55J IDT, 7024S55J Datasheet
7024S55J
Specifications of 7024S55J
Related parts for 7024S55J
7024S55J Summary of contents
Page 1
... BUSY outputs and INT outputs are non-tri-stated push-pull. ©2008 Integrated Device Technology, Inc. HIGH-SPEED DUAL-PORT STATIC RAM IDT7024 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M for BUSY output flag on Master M for BUSY input on Slave ...
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... The IDT7024 is packaged in a ceramic 84-pin PGA, an 84-pin Flatpack and PLCC, and a 100-pin TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability ...
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... I I/O I/O I R/W GND 12L 73 V 14L CC IDT7024G G84-3 (4) 74 GND 84-Pin PGA Top View ( SEM GND GND I/O I/O I/O R/W 9R 10R 13R 15R ...
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... V CC GND o -65 to +135 -65 to +150 C NOTES > -1.5V for pulse width less than 10ns must not exceed Vcc + 10%. TERM 2740 tbl 05 > Vcc + 10% TERM . 6.42 4 Mode 0-7 Deselcted: Power-Down Both Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only ...
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... IDT7024S/L High-Speed Dual-Port Static RAM Capacitance (T = +25° 1.0MHz) A Symbol Parameter Conditions C Input Capacitance IN C Output Capacitance V OUT NOTES: 1. This parameter are determined by device characterization, but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from from 3V to 0V. ...
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... IDT7024S/L High-Speed Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter Dynamic Operating CC Current Outputs Disabled SEM = V (Both Ports Active MAX Standby Current SB1 R SEM (Both Ports - TTL R Level Inputs MAX ...
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... IDT7024S/L High-Speed Dual-Port Static RAM Data Retention Waveform 4. CDR Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT BUSY INT 775Ω Figure 1. AC Output Test Load ...
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... IDT7024S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE (3) t Byte Enable Access Time ABE t Output Enable Access Time ...
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... IDT7024S/L High-Speed Dual-Port Static RAM Waveform of Read Cycles ADDR CE OE UB, LB R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, CE, OE, LB, or UB. 2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB. delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has 3 ...
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... Symbol WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW (3) t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write DW (1,2) t Output High-Z Time HZ (4) t Data Hold Time DH t ...
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... This parameter is guaranted by device characterization, but is not production tested. Transition is measured 0mV steady state with the Output Test Load (Figure 2 during R/W controlled write cycle, the write pulse width must be the larger placed on the bus for the required t ...
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... IDT7024S/L High-Speed Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM I R/W OE NOTES & for the duration of the above timing (both write and read cycle “DATA VALID” ...
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... IDT7024S/L High-Speed Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter BUSY TIMING (M BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Match t BDA BUSY Access Time from Chip Enable Low ...
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... IDT7024S/L High-Speed Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins ...
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... IDT7024S/L High-Speed Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing (M (1) IH ADDR "A" t APS ADDR " ...
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... IDT7024S/L High-Speed Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" "A" R/W "A" INT "B" ADDR "B" "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. ...
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... Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7024. 2. There are eight semaphore flags written to via I SEM = access the Semaphores ...
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... BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7024 RAM the BUSY pin is an output if the part is used as a master (M/S pin = V the BUSY pin is an input if the part used as a slave (M/S pin = V in Figure 3 ...
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... Using Semaphores—Some Examples Perhaps the simplest application of semaphores is their application as resource markers for the IDT7024’s Dual-Port RAM. Say the RAM was to be divided into two blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could ...
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... This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. SEMAPHORE SEMAPHORE REQUEST FLIP FLOP READ Figure 4. IDT7024 Semaphore Logic 6. PORT WRITE SEMAPHORE ...
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... Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations 6/4/99: Changed drawing format Page 1 Corrected DSC number 4/4/00: Replaced IDT logo Page 6 Corrected typo in Data Retention chart Changed ±500mV to 0mV in notes 5/19/00: Page 3 Clarified T A Page 4 Increased storage temperature parameter Pages 5 and 6 DC Electrical parameters– ...
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... Page 21 Added Industrial to 20ns ordering information 07/25/05: Page 1 Added green availability to features Page 21 Added green indicator to ordering information Page 1 & 21 Replaced old IDT ® logo with the new IDT Page 21 Updated address and phone contact information 10/29/08: Page 21 Removed "IDT" from orderable part number ...