71V3558S166PFGI IDT, 71V3558S166PFGI Datasheet - Page 13

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71V3558S166PFGI

Manufacturer Part Number
71V3558S166PFGI
Description
SRAM
Manufacturer
IDT
Datasheet

Specifications of 71V3558S166PFGI

Rohs
yes
Part # Aliases
IDT71V3558S166PFGI
Read Operation with Clock Enable Used
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE
Write Operation with Clock Enable Used
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Cycle
Cycle
n+2
n+3
n+4
n+5
n+6
n+7
n+2
n+3
n+4
n+5
n+6
n+7
n+1
n+1
n
n
Address
Address
A
A
A
A
A
A
A
A
A
A
X
X
X
X
X
X
0
2
3
4
0
2
3
4
1
1
1
1
= L, CE
= L, CE
R/W
R/W
X
X
X
X
X
X
H
H
H
H
H
L
L
L
L
L
2
2
= L and CE
= L and CE
ADV/LD
ADV/LD
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
2
2
= H. CE = H is defined as CE
= H. CE = H is defined as CE
CE
CE
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
(2)
(2)
CEN
CEN
L
H
L
H
H
L
L
L
L
H
L
H
H
L
L
L
1
1
BWx
BWx
= H, CE
= H, CE
6.42
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
13
2
2
= H or CE
= H or CE
OE
OE
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
(1)
(1)
2
2
= L.
= L.
I/O
I/O
Q
Q
Q
Q
D
D
Q
D
X
X
X
X
X
X
X
X
0
0
0
2
0
1
2
1
Commercial and Industrial Temperature Ranges
Comments
Clock n+1 Ignored
Clock Valid
Clock Ignored. Data Q
Clock Ignored. Data Q
Comments
Clock n+1 Ignored.
Clock Valid.
Clock Ignored.
Clock Ignored.
Address and Control meet setup
Address A
Address A
Address A
Address and Control meet setup.
Write Data D
Write Data D
Write Data D
0
1
2
Read out (bus trans.)
Read out (bus trans.)
Read out (bus trans.)
0
1
2
0
0
is on the bus.
is on the bus.
5281 tbl 17
5281 tbl 18

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