71V3558SA166BQG IDT, 71V3558SA166BQG Datasheet - Page 10

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71V3558SA166BQG

Manufacturer Part Number
71V3558SA166BQG
Description
SRAM
Manufacturer
IDT
Datasheet

Specifications of 71V3558SA166BQG

Product Category
SRAM
Rohs
yes
Part # Aliases
IDT71V3558SA166BQG
Interleaved Burst Sequence Table (LBO=V
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst Sequence Table (LBO=V
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram
NOTES:
1. This assumes CEN, CE
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay
First Address
Second Address
Fourth Address
First Address
Second Address
Fourth Address
Third Address
Third Address
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
from the rising edge of clock.
(R/W, ADV/LD, BWx)
I/O [0:31], I/O P[1:4]
CONTROL
ADDRESS
(A0 - A16)
CLOCK
DATA
CYCLE
(1)
(1)
(2)
(2)
(2)
1
, CE
2
, CE
D/Q27
2
n+29
C29
A29
are all true.
D/Q28
n+30
C30
A30
A1
A1
0
0
0
0
1
1
1
1
Sequence 1
Sequence 1
(1)
D/Q29
n+31
C31
A31
A0
A0
0
0
0
0
1
1
1
1
D/Q30
n+32
C32
A32
6.42
10
A1
A1
0
0
0
0
1
1
1
1
SS
Sequence 2
Sequence 2
)
D/Q31
n+33
C33
A33
A0
A0
DD
0
0
0
0
1
1
1
1
Commercial and Industrial Temperature Ranges
)
D/Q32
n+34
C34
A34
A1
A1
0
0
0
0
1
1
1
1
Sequence 3
Sequence 3
D/Q33
n+35
C35
A35
A0
A0
0
0
0
0
1
1
1
1
D/Q34
n+36
A36
C36
A1
A1
0
0
0
0
1
1
1
1
Sequence 4
Sequence 4
5281 drw 03
D/Q35
n+37
A37
C37
5281 tbl 10
A0
A0
5281 tbl 11
0
0
0
0
1
1
1
1
,

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