71V3558SA133BQGI IDT, 71V3558SA133BQGI Datasheet - Page 2

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71V3558SA133BQGI

Manufacturer Part Number
71V3558SA133BQGI
Description
SRAM
Manufacturer
IDT
Datasheet

Specifications of 71V3558SA133BQGI

Rohs
yes
Part # Aliases
IDT71V3558SA133BQGI
Description continued
mode, the IDT71V3556/58 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
Pin Definition
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
I/O
The IDT71V3556/58 has an on-chip burst counter. In the burst
BW
CE
I/O
Symbol
ADV/LD
A
TRST
V
CEN
P1
TMS
R/W
CLK
LBO
TCK
TDO
CE
V
V
0
1
OE
TDI
0
1
ZZ
DDQ
-A
, CE
-I/O
-BW
DD
SS
-I/O
2
17
31
P4
4
2
Linear Burst Order
Test Mode Select
Data Input/Output
Test Data Output
Advance / Load
Address Inputs
Test Data Input
Individual Byte
Write Enables
Output Enable
Power Supply
Power Supply
Pin Function
Clock Enable
Chip Enables
Read / Write
Sleep Mode
Chip Enable
JTAG Reset
Test Clock
(Optional)
Ground
Clock
(1)
N/A
N/A
N/A
I/O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Active
LOW
LOW
LOW
HIGH
LOW
LOW
LOW
HIGH
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip
deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter
is advanced for any burst that was in progress. The external addresses are ignored when ADV/ LD is sampled
high.
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are
ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
(When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW
sampled high. The appro priate byte(s) of data are written into the device two cycles later. BW
Synchronous active low chip enable. CE
Synchronous active high chip enable. CE
polarity but otherwise identical to CE
respect to the rising edge of CLK.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low
are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
Optional Asynchronous JTAG reset. Can be used to reset the TAP co ntroller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.
Synchronous sleep mode inp ut. ZZ HIGH will gate the CLK internally and power down the IDT71V3556/3558 to
its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
Ground.
ADV/LD low, CEN low, and true chip enables.
ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it
to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is
tied low if always doing write to the entire 36-bit word.
CE
The ZBT
This is the clock input to the IDT71V3556/58. Except for OE, all timing references for the device are made with
triggered by the rising edge of CLK.
the Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
Asynchronous output enable. OE must be low to read data from the 71V3556/58. When OE is high the I/O pins
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
3.3V core power supply.
3.3V I/O Supply.
2
sampled high or CE
TM
has a two cycle de select, i.e., the data bus will tri-state two clo ck cycles after deselect is initiated.
6.42
2
2
sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle.
external address (ADV/LD = LOW) or increment the internal burst
counter (ADV/LD = HIGH).
CMOS process and are packaged in a JEDEC standard 14mm x
20mm 100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball
grid array (BGA) and a 165 fine pitch ball grid array (fBGA).
The IDT71V3556/58 SRAMs utilize IDT's latest high-performance
1
and CE
1
2
and CE
is used with CE
2
.
Commercial and Industrial Temperature Ranges
2
are used with CE
1
and CE
2
2
to enable the chip. CE
to enable the IDT71V3556/58. (CE
1
-BW
4
) must be valid. The byte
2
1
has inverted
-BW
4
can all be
1
5281 tbl 02
or

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