71V3558SA133BQGI IDT, 71V3558SA133BQGI Datasheet - Page 9

• Manufacturer Part Number: 71V3558SA133BQGI
• Description: SRAM
• Manufacturer: IDT

Specifications of 71V3558SA133BQGI

• Rohs: yes
• Part # Aliases: IDT71V3558SA133BQGI

Synchronous Truth Table
NOTES:
1. L = V
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst
3. Deselect cycle is initiated when either (CE
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/Os remains
5. To select the chip requires CE
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes
NOTES:
1. L = V
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
READ
NO WRITE
WRITE ALL BYTES
WRITE BYTE 1 (I/O[0:7], I/O
WRITE BYTE 2 (I/O[8:15], I/O
WRITE BYTE 3 (I/O[16:23], I/O
WRITE BYTE 4 (I/O[24:31], I/O
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ ™ ™ ™ ™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
CEN
cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
two cycles after deselect is initiated.
unchanged.
H
L
L
L
L
L
L
IL
IL
, H = V
, H = V
R/W
H
X
X
X
X
X
L
IH
IH
, X = Don’t Care.
, X = Don’t Care.
Deselect
Enable
Chip
Select
Select
X
X
X
X
(5)
P1
P2
1
)
P3
P4
OPERATION
(2)
= L, CE
)
(2)
)
)
(2,3)
(2,3)
ADV/LD
X
L
L
H
H
L
H
2
= L, CE
1
, or CE
2
Valid
Valid
BWx
2
= H on these chip enables. Chip is deselected if any one of the chip enables is false.
X
X
X
X
X
is sampled high or CE
(1)
ADDRESS
External
External
Internal
Internal
USED
X
X
X
(1)
2
is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state
6.42
DESELECT / NOOP
PREVIOUS CYCLE
9
LOAD WRITE /
BURST WRITE
LOAD READ /
BURST READ
R/W
H
L
L
L
L
L
L
X
X
X
X
BW
Commercial and Industrial Temperature Ranges
X
L
L
H
H
H
H
1
(Advance burst counter)
(Advance burst counter)
DESELECT or STOP
CURRENT CYCLE
BURST WRITE
BURST READ
LOAD WRITE
LOAD READ
SUSPEND
BW
NOOP
X
L
H
L
H
H
H
2
(4)
(3)
BW
(2)
(2)
X
H
H
H
H
L
L
3
(3)
(2 cycles later)
Previous Value
D
Q
D
Q
HiZ
HiZ
I/O
BW
(7)
(7)
(7)
(7)
X
H
H
H
H
L
L
5281 tbl 08
5281 tbl 09
4
(3)