IS42S16400D-7TL ISSI, Integrated Silicon Solution Inc, IS42S16400D-7TL Datasheet

IC SDRAM 64MBIT 143MHZ 54TSOP

IS42S16400D-7TL

Manufacturer Part Number
IS42S16400D-7TL
Description
IC SDRAM 64MBIT 143MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet

Specifications of IS42S16400D-7TL

Package / Case
54-TSOP II
Memory Size
64M (4M x 16)
Format - Memory
RAM
Memory Type
SDRAM
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Data Bus Width
16 bit
Organization
1 Mbit x 16
Maximum Clock Frequency
143 MHz
Access Time
7 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
100 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
706-1019

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS42S16400D-7TL
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS42S16400D-7TL
Manufacturer:
ISSI
Quantity:
504
Part Number:
IS42S16400D-7TL
Manufacturer:
ISSI
Quantity:
20 000
Part Number:
IS42S16400D-7TLI
Manufacturer:
ISSI
Quantity:
20 000
IS42S16400D
FEATURES
• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to a
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
• Programmable burst sequence:
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
• Burst termination by burst stop and precharge
• Byte controlled by LDQM and UDQM
• Industrial temperature availability
• Package: 400-mil 54-pin TSOP II, 60-ball fBGA
• Lead-free package is available
PIN DESCRIPTIONS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/21/07
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
A0-A11
BA0, BA1
DQ0 to DQ15
CLK
CKE
CS
RAS
CAS
positive clock edge
– (1, 2, 4, 8, full page)
Sequential/Interleave
operations capability
command
Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
OVERVIEW
ISSI
as 1,048,576 bits x 16-bit x 4-bank for improved performance.
The synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
WE
LDQM
UDQM
V
GND
V
GND
NC
DD
DD
's 64Mb Synchronous DRAM IS42S16400D is organized
Q
Q
GNDQ
GNDQ
VDDQ
VDDQ
LDQM
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VDD
CAS
RAS
VDD
BA0
BA1
A10
WE
CS
A0
A1
A2
A3
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
Ground for DQ Pin
No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NOVEMBER 2007
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
GND
DQ15
GNDQ
DQ14
DQ13
VDDQ
DQ12
DQ11
GNDQ
DQ10
DQ9
VDDQ
DQ8
GND
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
GND
1

Related parts for IS42S16400D-7TL

IS42S16400D-7TL Summary of contents

Page 1

... Rev. E 11/21/07 NOVEMBER 2007 OVERVIEW ISSI 's 64Mb Synchronous DRAM IS42S16400D is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATIONS ...

Page 2

... IS42S16400D GENERAL DESCRIPTION The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 columns by 16 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode ...

Page 3

... IS42S16400D PIN CONFIGURATION PACKAGE CODE BALL FBGA (Top View) (10 6.4 mm Body, 0.65 mm Ball Pitch PIN DESCRIPTIONS A0-A11 Row Address Input A0-A7 Column Address Input BA0, BA1 Bank Select Addresses DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select ...

Page 4

... IS42S16400D PIN FUNCTIONS Symbol TSOP Pin No. Type A0-A11 Input Pin 22, 35 BA0, BA1 20, 21 Input Pin CAS 17 Input Pin CKE 37 Input Pin CLK 38 Input Pin CS 19 Input Pin DQ0 10, DQ Pin DQ15 11,13, 42, 44, 45, 47, 48, 50, 51, 53 LDQM, 15, 39 Input Pin ...

Page 5

... IS42S16400D FUNCTION (In Detail) A0-A11 are address inputs sampled during the ACTIVE (row-address A0-A11) and READ/WRITE command (A0-A7 with A10 defining auto PRECHARGE). A10 is sampled during a PRECHARGE command to determine if all banks are to be PRECHARGED (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command ...

Page 6

... IS42S16400D enabled or disabled. AUTO PRECHARGE does not apply except in full-page burst mode. Upon completion of the READ or WRITE burst, a precharge of the bank/row that is addressed is automatically performed. AUTO REFRESH COMMAND This command executes the AUTO REFRESH operation. The row address and bank to be refreshed are automatically generated during this operation ...

Page 7

... IS42S16400D TRUTH TABLE – COMMANDS AND DQM OPERATION FUNCTION COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank/column, start READ burst) WRITE (Select bank/column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH ...

Page 8

... IS42S16400D TRUTH TABLE – CKE (1-4) CURRENT STATE COMMANDn Power-Down X Self Refresh X Clock Suspend X (5) Power-Down COMMAND INHIBIT or NOP (6) Self Refresh COMMAND INHIBIT or NOP (7) Clock Suspend X All Banks Idle COMMAND INHIBIT or NOP All Banks Idle AUTO REFRESH Reading or Writing VALID See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n NOTES: 1. CKEn is the logic state of CKE at clock edge n ...

Page 9

... IS42S16400D NOTE: 1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table - CKE) and after t previous state was SELF REFRESH). 2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state ...

Page 10

... IS42S16400D TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m CURRENT STATE COMMAND (ACTION) Any COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Idle Any Command Otherwise Allowed to Bank m Row ACTIVE (Select and activate row) Activating, READ (Select column and start READ burst) ...

Page 11

... IS42S16400D 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been inter- rupted by bank m’s burst. ...

Page 12

... IS42S16400D ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD MAX V Maximum Supply Voltage for Output Buffer DDQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS T Operating Temperature OPR T Storage Temperature STG DC RECOMMENDED OPERATING CONDITIONS ...

Page 13

... IS42S16400D DC ELECTRICAL CHARACTERISTICS Symbol Parameter I Input Leakage Current IL I Output Leakage Current OL V Output High Voltage Level Output Low Voltage Level OL I Operating Current (1,2) CC1 I Precharge Standby Current CC2P I (In Power-Down Mode) CC2PS (3) I Precharge Standby Current CC2N I (In Non Power-Down Mode) ...

Page 14

... IS42S16400D AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time CK3 t CK2 (4,6) t Access Time From CLK AC3 t AC2 t CLK HIGH Level Width CHI t CLK LOW Level Width CL t Output Data Hold Time (6) OH3 t OH2 t Output LOW Impedance Time LZ (5) t Output HIGH Impedance Time ...

Page 15

... IS42S16400D OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t READ/WRITE command to READ/WRITE command CCD t CKE to clock disable or power-down entry mode CKED t CKE to clock enable or power-down exit setup mode PED t DQM to input data delay DQD t DQM to data mask during WRITEs ...

Page 16

... IS42S16400D FUNCTIONAL DESCRIPTION The 64Mb SDRAMs (1 Meg banks) are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; ...

Page 17

... IS42S16400D REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE ...

Page 18

... IS42S16400D Burst Length Read and write accesses to the SDRAM are burst ori- ented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length determines the maximum number of column loca- tions that can be accessed for a given READ or WRITE command. Burst lengths locations are ...

Page 19

... IS42S16400D CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge ...

Page 20

... IS42S16400D OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). ...

Page 21

... IS42S16400D READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst ...

Page 22

... IS42S16400D possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until the row precharge time is hidden during the access of the last data element(s). ...

Page 23

... IS42S16400D Consecutive READ Bursts T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. E 11/21/ NOP NOP NOP READ BANK, COL n+1 D OUT OUT T2 T3 ...

Page 24

... IS42S16400D Random READ Accesses T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - READ READ READ BANK, BANK, BANK, COL b COL m COL OUT OUT CAS Latency - READ READ READ NOP BANK, BANK, BANK, COL b COL m ...

Page 25

... IS42S16400D RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ Integrated Silicon Solution, Inc. — www.issi.com Rev. E 11/21/ NOP NOP NOP NOP n+1 D n+2 OUT OUT ...

Page 26

... IS42S16400D READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP PRECHARGE cycle BANK (a or all n+1 D n+2 D OUT OUT OUT NOP NOP NOP PRECHARGE ...

Page 27

... IS42S16400D READ Burst Termination T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. E 11/21/ BURST NOP NOP NOP TERMINATE n+1 D OUT OUT BURST NOP ...

Page 28

... IS42S16400D WRITEs WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE Command CLK HIGH - Z CKE CS RAS CAS WE A0-A7 COLUMN ADDRESS A8, A9, A11 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...

Page 29

... IS42S16400D WRITE Burst COMMAND ADDRESS WRITE to WRITE COMMAND Random WRITE Cycles COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. E 11/21/ CLK WRITE NOP NOP BANK, COL n CLK WRITE NOP BANK, ADDRESS COL n DON'T CARE CLK WRITE WRITE WRITE BANK, BANK, ...

Page 30

... IS42S16400D WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL NOP READ NOP BANK, COL b D n+1 IN CAS Latency - NOP NOP ACTIVE PRECHARGE BANK BANK all n+1 IN CAS Latency - 2 Integrated Silicon Solution, Inc. — www.issi.com ...

Page 31

... IS42S16400D WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS Integrated Silicon Solution, Inc. — www.issi.com Rev. E 11/21/ NOP NOP PRECHARGE BANK (a or all n+1 IN CAS Latency - CLK BURST WRITE TERMINATE BANK, COL DON'T CARE ...

Page 32

... IS42S16400D PRECHARGE The PRECHARGE command (see figure) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t the PRECHARGE command is issued. Input A10 deter- mines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1 select the bank ...

Page 33

... IS42S16400D CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. ...

Page 34

... IS42S16400D BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation ( ...

Page 35

... IS42S16400D WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after t where t begins when the READ to bank m is registered. ...

Page 36

... IS42S16400D INITIALIZE AND LOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 100µs Min. ...

Page 37

... IS42S16400D POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles Precharge all All banks idle, enter active banks power-down mode CAS latency = 2, 3 Integrated Silicon Solution, Inc. — ...

Page 38

... IS42S16400D CLOCK SUSPEND MODE CLK CKS CKH CKS CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM/ DQML, DQMH (2) A0-A9, A11 COLUMN A10 BA0, BA1 BANK DQ Notes: 1. CAS latency = 3, burst length = and A = "Don't Care" CKH NOP NOP NOP m+1 ...

Page 39

... IS42S16400D AUTO-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z CAS latency = 2, 3 Integrated Silicon Solution, Inc. — www.issi.com Rev. E 11/21/ Auto NOP ...

Page 40

... IS42S16400D SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM/ DQML, DQMH A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High Precharge all active banks refresh mode CAS latency = CKS t RAS Auto Refresh RP Enter self ...

Page 41

... IS42S16400D READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. CAS latency = 2, burst length = and A = " ...

Page 42

... IS42S16400D READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. CAS latency = 2, burst length = and A = "Don't Care" ...

Page 43

... IS42S16400D SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW DISABLE AUTO PRECHARGE BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. CAS latency = 2, burst length = and A = "Don't Care" ...

Page 44

... IS42S16400D SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. CAS latency = 2, burst length = and A = "Don't Care" NOP NOP ...

Page 45

... IS42S16400D ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1. CAS latency = 2, burst length = 4 2 ...

Page 46

... IS42S16400D READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN A10 ROW BA0, BA1 BANK BANK DQ t RCD Notes: 1. CAS latency = 2, burst length = full page and A = "Don't Care" ...

Page 47

... IS42S16400D READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD Notes: 1. CAS latency = 2, burst length = and A = " ...

Page 48

... IS42S16400D WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. burst length = and A = "Don't Care" ...

Page 49

... IS42S16400D WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK RCD t RAS t RC Notes: 1. burst length = and A = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev ...

Page 50

... IS42S16400D SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. burst length = and A = "Don't Care" ...

Page 51

... IS42S16400D SINGLE WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND (3) ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1. burst length = and A = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev ...

Page 52

... IS42S16400D ALTERNATING BANK WRITE ACCESS CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1. burst length = 4 2 ...

Page 53

... IS42S16400D WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1. burst length = full page and A = "Don't Care" Integrated Silicon Solution, Inc. — www.issi.com Rev ...

Page 54

... IS42S16400D WRITE - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1. burst length = and A = "Don't Care" WRITE NOP NOP t t CMS CMH (2) COLUMN m ENABLE AUTO PRECHARGE ...

Page 55

... IS42S16400D-6TL 400-mil TSOP II, Lead-free IS42S16400D-6BL 60-ball fBGA, Lead-free IS42S16400D-7T 400-mil TSOP II IS42S16400D-7TL 400-mil TSOP II, Lead-free IS42S16400D-7BL 60-ball fBGA, Lead-free Order Part No. Package IS42S16400D-6TLI 400-mil TSOP II, Lead-free IS42S16400D-6BLI 60-ball fBGA, Lead-free IS42S16400D-7TI 400-mil TSOP II IS42S16400D-7TLI 400-mil TSOP II, Lead-free IS42S16400D-7BLI 60-ball fBGA, Lead-free 55 ...

Page 56

PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (60-Ball SEATING PLANE mBGA - 10.1mm x 6.4mm ...

Page 57

PACKAGING INFORMATION Plastic TSOP 54–Pin, 86-Pin Package Code: T (Type II Plastic TSOP (T - Type II) Millimeters Symbol Min Max Ref. Std. No. Leads ( — 1.20 — A1 0.05 0.15 A2 ...

Related keywords