71V2556SA100BG IDT, 71V2556SA100BG Datasheet

71V2556SA100BG

Manufacturer Part Number

71V2556SA100BG

Description

SRAM

Manufacturer

IDT

Datasheet

1.71V2556S150PFG.pdf (23 pages)

Specifications of 71V2556SA100BG

Part # Aliases

IDT71V2556SA100BG

Current page: 1 of 23
Download datasheet (344Kb)

Features

◆ ◆ ◆ ◆ ◆

Description

synchronous SRAM. It is designed to eliminate dead bus cycles when

turning the bus around between reads and writes, or writes and reads.

Thus, they have been given the name ZBT

Pin Description Summary

/ R W

B L

C T

D T

Z Z

O /

128K x 36 memory configurations

Supports high performance system speed - 166 MHz

(3.5 ns Clock-to-Data Access)

ZBT

cycles

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

Three chip enables for simple depth expansion

3.3V power supply (±5%), 2.5V I/O Supply (V

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

complaint)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP) and 119 ball grid array (BGA)

The IDT71V2556 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

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/ V

I -

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O /

D L

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Feature - No dead cycles between write and read

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O /

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) control (May tie active)

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128K x 36

3.3V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

, or Zero Bus Turnaround.

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DDQ)

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registers. Output enable is the only asynchronous signal and can be used

to disable the outputs at any given time.

suspended as long as necessary. All synchronous inputs are ignored

when (CEN) is high and the internal device registers will hold their previous

values.

to deselect the device when desired. If any one of these three are not

asserted when ADV/LD is low, no new memory operation can be initiated.

However, any pending data transfers (reads or writes) will be completed.

The data bus will tri-state two cycles after chip is deselected or a write is

initiated.

IDT71V2556 can provide four cycles of data for a single address

presented to the SRAM. The order of the burst sequence is defined by the

LBO input pin. The LBO pin selects between linear and interleaved burst

sequence. The ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =

HIGH).

process and are packaged in a JEDEC standard 14mm x 20mm 100-pin

thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA).

cycle, and two cycles later the associated data cycle occurs, be it read

or write.

The IDT71V2556 contains data I/O, address and control signal

A Clock Enable (CEN) pin allows operation of the IDT71V2556 to be

There are three chip enable pins (CE

The IDT71V2556 has an on-chip burst counter. In the burst mode, the

The IDT71V2556 SRAMs utilize IDT's latest high-performance CMOS

Address and control signals are applied to the SRAM during one clock

u S

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p p

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t u

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IDT71V2556SA/XSA

IDT71V2556S/XS

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APRIL 2011

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Related parts for 71V2556SA100BG

71V2556SA100BG Summary of contents

Page 1

... Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V2556 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values ...

Page 2

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs (1) Pin Definitions ...

Page 3

... NOTES (min.) = –1.0V for pulse width less than (max.) = +6.0V for pulse width less than Address D Q Control D Q Control Logic Clk Gate JTAG TDO (SA Version ...

Page 4

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Recommended Operating Temperature and Supply Voltage ° ° ...

Page 5

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Absolute Maximum Ratings ...

Page 6

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Pin Configuration — 128K x 36, 119 BGA DDQ I/O 16 I/O P3 I/O I I/O DDQ 19 G I/O 20 I/O 21 I/O I DDQ DD K I/O 24 I/O 26 I/O I ...

Page 7

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Synchronous Truth Table ...

Page 8

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Interleaved Burst Sequence Table ...

Page 9

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles / ...

Page 10

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Burst Read Operation / ...

Page 11

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Read Operation with Clock Enable Used / ...

Page 12

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Read Operation with Chip Enable Used / ...

Page 13

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range ...

Page 14

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs AC Electrical Characteristics (V = 3.3V±5%, Commercial and Industrial Temperature Ranges ...

Page 15

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of Read Cycle Commercial and Industrial Temperature Ranges (1,2,3,4) 6.42 15 ...

Page 16

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of Write Cycles Commercial and Industrial Temperature Ranges (1,2,3,4,5) 6.42 16 ...

Page 17

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of Combined Read and Write Cycles Commercial and Industrial Temperature Ranges (1,2,3) 6.42 17 ...

Page 18

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of CEN Operation Commercial and Industrial Temperature Ranges (1,2,3,4) 6.42 18 ...

Page 19

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of CS Operation Commercial and Industrial Temperature Ranges (1,2,3,4) 6.42 19 ...

Page 20

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs JTAG Interface Specification (SA Version only JCL TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO ( 3) TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. 2. Device outputs = All device outputs except TDO. ...

Page 21

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs JTAG Identification Register Definitions (SA Version only ...

Page 22

... IDT71V2556, 128K x 36, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Timing Waveform of OE Operation OE DATA OUT NOTE read operation is assumed progress. Ordering Information XX XXXX Device Power Speed Package Type (1) t OHZ Process/ Temperature Range ...

Page 23

... Silver Creek Valley Rd San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc. Commercial and Industrial Temperature Ranges ...

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