7130LA20J IDT, 7130LA20J Datasheet

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7130LA20J

Manufacturer Part Number
7130LA20J
Description
SRAM
Manufacturer
IDT
Datasheet

Specifications of 7130LA20J

Part # Aliases
IDT7130LA20J
I/O
Features
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Functional Block Diagram
NOTES:
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
2. Open drain output: requires pullup resistor.
©2013 Integrated Device Technology, Inc.
0L
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55/100ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7130/IDT7140SA
– IDT7130/IDT7140LA
MASTER IDT7130 easily expands data bus width to 16-or-
more-bits using SLAVE IDT7140
IDT7140 (SLAVE): BUSY is input.
BUSY
- I/O
R/W
Active: 550mW (typ.)
Standby: 5mW (typ.)
Active: 550mW (typ.)
Standby: 1mW (typ.)
INT
OE
CE
A
A
7L
9L
0L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
CE
OE
L
L
L
10
Control
I/O
HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
ARBITRATION
INTERRUPT
MEMORY
ARRAY
LOGIC
and
1
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On-chip port arbitration logic (IDT7130 Only)
BUSY output flag on IDT7130; BUSY input on IDT7140
INT flag for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation–2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
Green parts available, see ordering information
Control
I/O
10
Decoder
Address
R/W
CE
OE
R
R
R
JANUARY 2013
IDT7130SA/LA
IDT7140SA/LA
2689 drw 01
OE
CE
R/W
I/O
BUSY
A
A
INT
DSC-2689/15
9R
0R
0R
R
R
R
R
(2)
-I/O
R
(1,2)
7R
,

Related parts for 7130LA20J

7130LA20J Summary of contents

Page 1

... OE L R/W L (2) INT L NOTES: 1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor. IDT7140 (SLAVE): BUSY is input. 2. Open drain output: requires pullup resistor. ©2013 Integrated Device Technology, Inc. HIGH SPEED DUAL-PORT STATIC SRAM On-chip port arbitration logic (IDT7130 Only) ◆ ...

Page 2

... High-Speed Dual-Port Static SRAM Description The IDT7130/IDT7140 are high-speed Dual-Port Static RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit Dual-Port RAM "MASTER" Dual-Port RAM together with the IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or- more-bit memory system applications results in full-speed, error- free operation without the need for additional discrete logic ...

Page 3

... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Pin Configurations (con't.) (1,2,3) 01/08/02 R/W BUSY INT I/O I/O I/O I/O I/O I/O I/O I/O GND NOTES: 1. All V pins must be connected to power supply All GND pins must be connected to ground supply. 3. P48-1 package body is approximately . . .19 in. C48-2 package body is approximately . 2. .15 in. ...

Page 4

... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Pin Configurations (1,2,3) (con't.) 01/22/13 INDEX I/O 3L NOTES: 1. All V pins must be connected to power supply All GND pins must be connected to ground supply. ...

Page 5

... PN64-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Military, Industrial and Commercial Temperature Ranges IDT7130/40TF (4) PP64-1 & PN64 64-Pin STQFP 40 64-Pin TQFP ...

Page 6

... V Input High Voltage IH V Input Low Voltage IL -65 to +150 C o NOTES (min.) > -1.5V for pulse width less than 10ns must not exceed Vcc + 10%. TERM 2689 tbl 01 Recommended Operating Temperature and Supply Voltage Grade > Vcc + 10%. TERM Military Commercial Industrial NOTES: Max ...

Page 7

... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter I Dynamic Operating and Current Outputs Disabled (Both Ports Active) ( MAX I Standby Current CE and SB1 L R (Both Ports - TTL ...

Page 8

... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Data Retention Characteristics Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Deselect to Data Retention Time CDR (3) t Operation Recovery Time R NOTES 2V +25°C, and is not production tested. ...

Page 9

... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 5V 1250Ω DATA OUT 775Ω 30pF* Figure 1. Output Test Load 5V 270Ω BUSY or INT 30pF* Figure 3 ...

Page 10

... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Output Enable Access Time AOE t Output Hold from Address Change ...

Page 11

... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of Read Cycle No. 1, Either Side ADDRESS PREVIOUS DATA VALID DATA OUT BUSY OUT NOTES and Address is valid prior to the coincidental with CE transition LOW delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations, BDD BUSY has no relationship to valid output data ...

Page 12

... R BAA LOW during a R/W controlled write cycle, the write pulse width must be the larger placed on the bus for the required HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse DW can be as short as the specified t ...

Page 13

... This parameter is determined by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2 LOW during a R/W controlled write cycle, the write pulse width must be the larger of t bus for the required HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t ...

Page 14

... Write Data Valid to Read Data Delay DDD (3) t Arbitration Priority Set-up Time APS t (4) BUSY Disable to Valid Data BDD BUSY INPUT TIMING (For SLAVE IDT 7140) (5) t Write to BUSY Input WB (6) t Write Hold After BUSY WH (2) t Write Pulse to Data Delay ...

Page 15

... R/W "B" NOTES must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master BUSY is asserted on port "B" blocking R/W , until BUSY "B" 3. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A". ...

Page 16

... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM Timing Waveform of BUSY Arbitration Controlled by CE Timing ADDR AND 'A' 'B' CE 'B' (2) t APS CE 'A' BUSY 'A' Timing Waveform by BUSY Arbitration Controlled by Address Match Timing t RC ADDR ADDRESSES MATCH 'A' (2) t APS ADDR 'B' t BAA BUSY ...

Page 17

... IDT7130SA/LA and IDT7140SA/LA High-Speed Dual-Port Static SRAM AC Electrical characteristics Over the Operating Temperature and Supply Voltage Range Symbol INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t Interrupt Reset Time INR NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). ...

Page 18

... MATCH MATCH (2) NOTES: 1. Pins BUSY and BUSY are both outputs for IDT7130 (master). Both are inputs for L R IDT7140 (slave). BUSY outputs on the IDT7130 are open drain, not push-pull X outputs. On slaves the BUSY input internally inhibits writes 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port ...

Page 19

... Thus on the IDT7130/IDT7140 RAMs the BUSY pin is an output if the part is Master (IDT7130), and the BUSY pin is an input if the part is a Slave (IDT7140) as shown ...

Page 20

... Changed drawing format 08/02/99: Page 2 Corrected package number in note 3 09/29/99: Page 2 Fixed pin 1 in DIP pin configuration 11/10/99: Page 1 & 18 Replaced IDT logo 06/23/00: Page 4 Increased storage temperature parameters Clarified T Page 5 DC Electrical parameters–changed wording from "open" to "disabled" Page 10 Changed ±500mV to 0mV in notes 01/08/02: Page 1 Added Ceramic Flatpack to 48-pin package offerings Page 2 & ...

Page 21

... CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Military, Industrial and Commercial Temperature Ranges Added industrial temp for 25ns to DC & AC Electrical Characteristics Removed industrial temp for 35ns to DC & AC Electrical Characteristics ...

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