CY7C1021DV33-10ZSXAT Cypress Semiconductor, CY7C1021DV33-10ZSXAT Datasheet
CY7C1021DV33-10ZSXAT
Specifications of CY7C1021DV33-10ZSXAT
Related parts for CY7C1021DV33-10ZSXAT
CY7C1021DV33-10ZSXAT Summary of contents
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... HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA packages. DATA IN DRIVERS ...
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... I CY7C1021DV33 48-ball VFBGA Top View BHE I/O I I/O A I/O V ...
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... Test Conditions T = 25 MHz 3 Test Conditions Still Air, soldered × 4.5 inch, four-layer printed circuit board CY7C1021DV33 Ambient V CC Temperature 3.3 V 0.3 V –40 °C to +85°C –40 °C to +85°C –10 (Ind’l/Auto-A) Min. Max. 2.4 0.4 2 ...
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... AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05460 Rev. *G [4] 3 30 pF* GND Rise Time: 1 V/ns High-Z characteristics: R 317 3.3 V OUTPUT 351 (c) CY7C1021DV33 ALL INPUT PULSES 90% 90% 10% 10% Fall Time: 1 V/ns (b) Page ...
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... Document #: 38-05460 Rev. *G [5] Description [8] [7, 8] [8] [7, 8] [8] [7, 8] values until the first memory access can be performed less than less than t , and t HZCE LZCE HZOE LZOE CY7C1021DV33 -10 (Ind’l/Auto-A) Min. Max. 100 ...
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... OHA [13, 14 ACE t DOE t LZOE t DBE t LZBE 50% > 50 s or stable at V ramp from CC(min.) CC(min CY7C1021DV33 Min. Max. 2 – 0 Industrial < DATA VALID t HZOE t HZCE t HZBE HIGH IMPEDANCE DATA VALID t PD 50% > ...
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... If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05460 Rev. *G [15, 16 SCE PWE t BW DATA IN VALID PWE t SCE DATA IN VALID . IH CY7C1021DV33 Page ...
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... Data Out Read – Upper bits only Data In Write – All bits High-Z Write – Lower bits only Data In Write – Upper bits only High-Z Selected, outputs disabled High-Z Selected, outputs disabled CY7C1021DV33 LZWE Mode Power Standby (I Active (I ...
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... ZSX = 44-pin TSOP Type II (Pb-free) BVX = 48-ball VFBGA (Pb-free) Speed V33 = Voltage range ( 3 C9 Technology 1 = Data width × 16-bits 02 = 1-Mbit density 1 = Fast Asynchronous SRAM family Technology Code CMOS 7 = SRAM CY = Cypress CY7C1021DV33 Operating Range Industrial Automotive-A Page ...
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... Package Diagrams Figure 1. 44-pin (400-Mil) Molded SOJ (51-85082) Figure 2. 44-pin Thin Small Outline Package Type II (51-85087) Document #: 38-05460 Rev. *G CY7C1021DV33 51-85082 *D 51-85087 *D Page ...
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... Package Diagrams (continued) Figure 3. 48-ball VFBGA ( mm) (51-85150) Document #: 38-05460 Rev. *G CY7C1021DV33 51-85150 *G Page ...
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... Document History Page Document Title: CY7C1021DV33, 1-Mbit (64K x 16) Static RAM Document Number: 38-05460 REV. ECN NO. Issue Date ** 201560 See ECN *A 233693 See ECN *B 263769 See ECN *C 307601 See ECN *D 520652 See ECN *E 2898399 03/24/2010 *F 3109897 12/14/2010 *G 3421856 10/25/2011 Document #: 38-05460 Rev. *G Orig ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05460 Rev. *G < cypress.com/go/plc cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB Revised October 25, 2011 CY7C1021DV33 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 Page ...