IC EEPROM 256KBIT 400KHZ 8SOIC

 

M24256-BWMN6TP

Manufacturer Part NumberM24256-BWMN6TP
DescriptionIC EEPROM 256KBIT 400KHZ 8SOIC
ManufacturerSTMicroelectronics
M24256-BWMN6TP datasheets

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Specifications of M24256-BWMN6TP

Format - MemoryEEPROMs - SerialMemory TypeEEPROM
Memory Size256K (32K x 8)Speed400kHz
InterfaceI²C, 2-Wire SerialVoltage - Supply2.5 V ~ 5.5 V
Operating Temperature-40°C ~ 85°CPackage / Case8-SOIC (3.9mm Width)
Density256KbInterface TypeSerial (I2C)
Organization32Kx8Access Time (max)900ns
Frequency (max)400KHzWrite ProtectionYes
Data Retention40YearOperating Supply Voltage (typ)3.3/5V
Package TypeSOICOperating Temp Range-40C to 85C
Supply Current5mAOperating Supply Voltage (min)2.5V
Operating Supply Voltage (max)5.5VOperating Temperature ClassificationIndustrial
MountingSurface MountPin Count8
Maximum Clock Frequency0.4 MHzAccess Time900 ns
Supply Voltage (max)5.5 VSupply Voltage (min)2.5 V
Maximum Operating Current5 mAMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
Operating Supply Voltage2.5 V, 5.5 VLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names497-8623-2
M24256-BWMN6TP
  
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Description
1
Description
The M24256-Bx devices are I
(EEPROM). They are organized as 32 K × 8 bits.
The M24256-DR also offers an additional page, named the Identification Page (64 bytes)
which can be written and (later) permanently locked in Read-only mode. This Identification
Page offers flexibility in the application board production line, as it can be used to store
unique identification parameters and/or parameters specific to the production line.
The device behaves as a slave in the I
synchronized by the serial clock. Read and Write operations are initiated by a Start
condition, generated by the bus master. The Start condition is followed by a Device Select
code and Read/Write bit (RW) (as described in
Inside this Device Select code, the 4-bit device type identifier code is (1010) for the M24256-
B and is (1011) for the M24256-D.
When writing data to the memory, the device inserts an acknowledge bit during the 9
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Figure 1.
Logic diagram
Table 1.
Signal names
Signal name
E0, E1, E2
SDA
SCL
WC
V
CC
V
SS
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M24256-BF, M24256-BR, M24256-BW, M24256-DR
2
C-compatible electrically erasable programmable memories
2
C-bus protocol, with all memory operations
Table
4), terminated by an acknowledge bit.
Function
Chip Enable
Serial Data
Serial Clock
Write Control
Supply voltage
Ground
Doc ID 6757 Rev 23
th
bit
Direction
Inputs
I/O
Input
Input