AT89LP51ED2-20MU Atmel, AT89LP51ED2-20MU Datasheet
AT89LP51ED2-20MU
Specifications of AT89LP51ED2-20MU
Related parts for AT89LP51ED2-20MU
AT89LP51ED2-20MU Summary of contents
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... Interrupt Priority • Nonvolatile Program and Data Memory – 64KB of In-System Programmable (ISP) Flash Program Memory – 4KB of EEPROM (AT89LP51ED2/ID2 Only) – 512-byte User Signature Array – Endurance: 10,000 Write/Erase Cycles – Serial Interface for Program Downloading – 2KB Boot ROM Contains Low Level Flash Programming Routines and a Default Serial Bootloader • ...
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Pin Configurations 1.1 44-lead TQFP/LQFP (†MOSI/CEX2/MISO) P1.5 (†MISO/CEX3/SCK) P1.6 (†SCK/CEX4/MOSI) P1.7 † SPI in remap mode ‡ AT89LP51ID2 Only 1.2 44-lead PLCC (†MOSI/CEX2/MISO) P1.5 (†MISO/CEX3/SCK) P1.6 (†SCK/CEX4/MOSI) P1.7 † SPI in remap mode ‡ AT89LP51ID2 Only AT89LP51RD2/ED2/ID2 Preliminary 2 ...
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VQFN/QFN/MLF † SPI in remap mode ‡ AT89LP51ID2 Only (†MOSI/CEX2/MISO) P1.5 (†MISO/CEX3/SCK) P1.6 (†SCK/CEX4/MOSI) P1.7 1.4 40-pin PDIP Note: 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary (DCL) RST 4 (RXD) P3.0 5 (SDA) P4.1 6 (TXD) P3.1 7 (INT0) ...
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... Pin Description Table 1-1. Atmel AT89LP51RD2/ED2/ID2 Pin Description Pin Number (1) VQFP VQFN PLCC PDIP Symbol RST P4.6 AT89LP51RD2/ED2/ID2 Preliminary 4 Type Description I/O P1 ...
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... Table 1-1. Atmel AT89LP51RD2/ED2/ID2 Pin Description Pin Number (1) VQFP VQFN PLCC PDIP Symbol GND POL P0.3 3714A–MICRO–7/11 ...
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... The AT89LP51ID2 is not available in the PDIP package 2. Overview The Atmel controller with 64KB of In-System Programmable Flash program memory. The AT89LP51ED2 and AT89LP51ID2 provide an additional 4KB of EEPROM for nonvolatile data storage. The devices are manufactured using Atmel's high-density nonvolatile memory technology and are compatible with the industry-standard 80C51 instruction set ...
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... The AT89LP51RD2/ED2/ID2 retains all of the standard features of the AT89C51RD2/ED2, including: 64KB of In-System Programmable Flash program memory, 4KB of EEPROM (AT89LP51ED2/ID2 Only), 256 bytes of RAM, 2KB of expanded RAM I/O lines, three 16-bit timer/counters, a Programmable Counter Array, a programmable hardware watchdog timer, a keyboard interface, a full-duplex enhanced serial port, a serial peripheral interface (SPI), on-chip crystal oscillator, and a four-level, ten-vector interrupt system ...
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... For more information, see Section 24.2 “User Configuration Fuses” on page AT89LP51RD2/ED2/ID2 Preliminary 8 Atmel AT89LP51RD2/ED2/ID2 Block Diagram Flash Code Boot ROM EEPROM 64KB 2KB (AT89LP51ED2/ID2) 8051 Single Cycle CPU with 12-cycle Compatiblity Port 0 Configurable I/O Port 1 Configurable I/O Port 2 Configurable I/O Port 3 ...
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Table 2-1. Fuse Name Clock Source A Clock Source B Oscillator Select X2 Mode Start-up Time Compatibility Mode XRAM Configuration Bootloader Jump Bit On-Chip Debug Enable In-System Programming Enable User Signature Programming Enable Default Port State Low Power Mode 2.2.2 ...
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... In Compatibility mode the Atmel cycle of the standard 8051 where instruction bytes are fetched every three system clock cycles. Execution times in this mode are identical to the Atmel AT89C51RD2/ED2/ID2. For greater per- formance the user can enable Fast mode by disabling the Compatibility fuse. In Fast mode the CPU fetches one code byte from memory every clock cycle instead of every three clock cycles ...
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Timer/Counters A common prescaler is available to divide the time base for Timer 0, Timer 1, Timer 2 and the WDT. The TPS Compatibility mode TPS machine cycle. The counting rate can be adjusted linearly from the system clock ...
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Security The AT89LP51RD2/ED2/ID2 does not support the external access pin (EA). Therefore it is not possible to execute from external program memory in address range 0000H–1FFFH. When the third Lockbit is enabled (Lock Mode 4) external program execution is ...
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... Indirectly addressable internal RAM and stack space Directly addressable I/O register space On-chip Extra RAM and extended stack space On-chip nonvolatile EEPROM data memory (AT89LP51ED2 and AT89LP51ID2 only) External data memory On-chip nonvolatile Flash program memory External program memory On-chip nonvolatile Flash signature array On-chip Bootloader ROM and Flash API 1 ...
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... ROM using shows the timing of the external program memory interface. ALE is emitted at a con- 01FF User Signature Array 0100 SIGEN=1 007F Atmel Signature Array 0000 FFFF Boot ROM (BOOT: 2KB) F800 F7FF ...
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Figure 3-2. Figure 3-3. In order for Fast mode to fetch externally, two wait states must be inserted for every clock cycle, increasing the instruction execution time by a factor of 3. However, due to other optimizations, external Fast mode ...
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... In addition to the 64K code space, the AT89LP51RD2/ED2/ID2 also supports a 512-byte User Signature Array and a 128-byte Atmel Signature Array that are accessible by the CPU. The Atmel Signature Array is initialized with the Device ID in the factory. The User Signature Array is available for user identification codes or constant parameter data. Data stored in the signature array is not secure. Security bits will disable writes to the array ...
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External Data Memory AT89LP microcontrollers support a 16-bit external memory address space for up to 64K bytes of external data memory (XDATA). The external memory space is accessed with the MOVX instructions. Some internal data memory resources are mapped ...
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Figure 3-7 a 16-bit linear address. Port 0 serves as a multiplexed address/data bus to the RAM. The Address Latch Enable strobe (ALE) is used to latch the lower address byte into an external reg- ister so that Port 0 ...
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Table 3-3. – Auxiliary Control Register AUXR AUXR = 8EH Not Bit Addressable (1) DPU WS1 Bit 7 6 Symbol Function ...
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Figure 3-9. CLK ALE Figure 3-10. CLK ALE Figure 3-11. Compatibility Mode External Data Memory Write Cycle (WS0 = 0) AT89LP51RD2/ED2/ID2 Preliminary 20 Fast Mode External Data Memory Write Cycle (WS = 00B SFR DPL ...
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Figure 3-12. Compatibility Mode External Data Memory Read Cycle (WS0 = 0) Figure 3-13. MOVX with One Wait State (WS = 01B) CLK ALE Figure 3-14. MOVX with Two Wait States (WS = 10B) CLK ...
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... EEPROM can be accessed only by 16-bit (MOVX @DPTR) addresses. MOVX @Ri instructions to the EEPROM address range will access data memory in the EDATA or XDATA spaces. Addresses above the EEPROM range are mapped to external data memory (XDATA). This feature is only available on AT89LP51ED2 and AT89LP51ID2. AT89LP51RD2/ED2/ID2 Preliminary 22 ...
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Read Protocol The following procedure is used to read data stored in the on-chip EEPROM. 1. Check EEBUSY flag (EECON.0) and wait for low if necessary 2. Disable interrupts if any interrupt routine accesses external data ...
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... EEPROM. The next write to occur with LDPG = 0 will write that byte and all previously loaded bytes to the EEPROM. The AT89LP51ED2/ID2 has a EEPROM buffer of 32 bytes. Address locations that are not loaded will remain untouched, i.e. no erase/write will occur. ...
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Figure 3-17. EEPROM Page Write of Five Bytes 3.5.3 Erase During a write sequence, individual EEPROM bytes are erased and then written in one atomic operation. The entire 4KB EEPROM is normally erased when a Chip Erase command is issued ...
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Extended Stack The AT89LP51RD2/ED2/ID2 provides an extended stack space for applications requiring addi- tional stack memory. By default the stack is located in the 256-byte IDATA space of internal data memory. The IDATA stack is referenced solely by the ...
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... Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 4-1. Atmel AT89LP51RD2/ED2/ID2 SFR Map and Reset Values ...
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Table 4-2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer SPX EFh Extended Stack Pointer DPL 82h Data Pointer Low Byte DPH 83h Data Pointer High ...
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Table 4-5. Interrupt SFRs Mnemonic Add Name IEN0 A8h Interrupt Enable Control 0 IEN1 B1h Interrupt Enable Control 1 IPH0 B7h Interrupt Priority Control High 0 IPL0 B8h Interrupt Priority Control Low 0 IPH1 B3h Interrupt Priority Control High 1 ...
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Table 4-8. Timer SFRs Mnemonic Add Name TCON 88h Timer/Counter 0 and 1 Control TMOD 89h Timer/Counter 0 and 1 Modes TCONB 91h Timer/Counter 0 and 1 Mode B TL0 8Ah Timer/Counter 0 Low Byte TH0 8Ch Timer/Counter 0 High ...
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Table 4-11. Keyboard Interface SFRs Mnemonic Add Name KBLS 9Ch Keyboard Level Selector KBE 9Dh Keyboard Input Enable KBF 9Eh Keyboard Flag Register KBMOD 9Fh Keyboard Mode Register Table 4-12. Flash/EEPROM Memory SFR Mnemonic Add Name BMSEL 92h Bank Mode ...
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Table 4-15. PCA SFRs (Continued) Mnemo -nic Add Name CCAPM3 DDh PCA Timer/Counter Mode 3 CCAPM4 DEh PCA Timer/Counter Mode 4 CCAP0H FAh PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0 CCAP1H FBh PCA ...
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Enhanced CPU The AT89LP51RD2/ED2/ID2 uses an enhanced 8051 CPU that runs times the speed of standard 8051 devices ( times the speed of X2 8051 devices). The increase in perfor- mance is ...
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Compatibility Mode Compatibility (12-Clock) mode is enabled by default from the factory or by setting the Compati- bility User Fuse. In Compatibility mode instruction bytes are fetched every three system clock cycles and the CPU operates with 6-state machine ...
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A block diagram of the MAC unit is shown in vided by the register pairs (AX,ACC) and (BX,B) where AX (E1H) and BX (F7H) hold the higher order bytes. The 16-by-16 bit multiplication is computed through partial products using the ...
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Figure 5- consequence of the MAC unit, the standard 8x8 MUL AB instruction can support signed multiplication. The SMLA and SMLB bits in DSPR control the multiplier’s interpretation of the ACC and B registers, allowing any combination of ...
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Enhanced Dual Data Pointers The AT89LP51RD2/ED2/ID2 provides two 16-bit data pointers: DPTR0 and DPTR1. The data pointers are used by several instructions to access the program or data memories. The Auxiliary 1 Register (AUXR1) and Data Pointer Configuration Register ...
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A summary of data pointer instructions with fast context switching is listed Table 5-3. Instruction JMP @A+DPTR MOV DPTR, #data16 MOV /DPTR, #data16 INC DPTR INC /DPTR MOVC A,@A+DPTR MOVC A,@A+/DPTR MOVX A,@DPTR MOVX A,@/DPTR MOVX @DPTR, A MOVX @/DPTR, ...
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Table 5-5. Data Pointer Auto-Update Update Operation for MOVX and MOVC (DPU1 = 1 & DPU0 = 1) DPD1 DPD0 DPTR 0 0 DPTR0 DPTR0 DPTR0 DPTR0-- Table 5-6. – Auxiliary Register 1 AUXR1 ...
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Data Pointer Operating Modes The Dual Data Pointers on the AT89LP51RD2/ED2/ID2 include three additional operating modes that affect data pointer based instructions. These modes are controlled by bits in DSPR. Note that these bits in DSPR should be cleared ...
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Circular Buffers The CBE0 and CBE1 bits in DSPR can configure DPTR0 and DPTR1, respectively, to operate in circular buffer mode. The AT89LP51RD2/ED2/ID2 maps circular buffers into two identically sized regions of EDATA/XDATA. These buffers can speed up convolution ...
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Table 5-10. Opcode • The /DPTR instructions provide support for the dual data pointer features described above (See • The ASR M, LSL M, CLR M and MAC ...
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System Clock The AT89LP51RD2/ED2 has a single system clock that is generated directly from one of three selectable clock sources: on-chip crystal oscillator A in high or low power operation, external clock source on XTAL1A, and the internal 8 ...
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Table 6-1. Clock Source A Fuse 1 Table 6-2. Clock Source B Fuse 1 6.1 Crystal Oscillator A When enabled, internal inverting oscillator amplifier A is connected between XTAL1A and XTAL2A for connection to an external quartz crystal or ceramic ...
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... RC Calibration Byte stored at byte 384 of the User Sig- nature Array. This location may be updated using the IAP interface external device programmer (User Signature location 0180H). See page 190. A copy of the factory calibration byte is stored at byte 8 of the Atmel Signature Array (0008H in SIG space). 6.4 Crystal Oscillator B (AT89LP51ID2) AT89LP51ID2 includes a second crystal oscillator for low-frequency (~32 KHz) operation ...
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Figure 6-5. Note: 6.5 External Clock Source B (AT89LP51ID2) The external clock option of AT89LP51ID2 disables the oscillator amplifier B and allows XTAL1B to be driven directly by an external clock source as shown in unconnected or used as general ...
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BEn bits in OSCCON. The oscillator selection at reset is controlled by the Oscillator Select user fuse (See loader Hardware Security Byte. The fuse sets the CKS, OscAEn and OscBEn bits as shown in Table 6-3. Table 6-3. Control Bit ...
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Registers Table 6-4. – Clock Selection Register CKSEL CKSEL = 85H (AT89LP51ID2 Only) Not Bit Addressable – – Bit 7 6 Symbol Function CKS Clock Select. Clear CKS to connect the system clock (CPU and peripherals) to the OSCB ...
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System Clock Prescaler The AT89LP51RD2/ED2/ID2 includes an 8-bit prescaler that allows the system clock to be divided down from the selected clock source by even numbers in the range 4–1020 in X1 mode and 2–510 in X2 mode. The ...
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Peripheral Clocks The base peripheral clock is the same as the CPU clock affected by both the X2 setting and the CKRL prescaler. However, individual peripherals can have their clock further modified using the Timer Prescaler in ...
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Symbol Function SIX2 UART Clock. In Compatibility Mode, clear for one system clock period per peripheral clock cycle and set for two clock periods per peripheral clock cycle (only valid when X2 = 1). In Fast Mode, clear for one ...
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Table 6-10. – Clock Control Register 1 CKCON1 CKCON1 = AFH Not Bit Addressable – – Bit 7 6 Symbol Function SPIX2 SPI Clock. In Compatibility Mode, clear for one system clock period per peripheral clock cycle and set for ...
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Reset During reset, all I/O Registers are set to their initial values, the port pins are set to their default ...
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Figure 7-2. Note: Table 7-1. SUT Fuse 1 7.2 Brown-out Reset The AT89LP51RD2/ED2/ID2 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V DD the BOD is nominally 2.0V. The purpose of the BOD is to ensure that if ...
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Figure 7-3. Time-out Internal Reset The AT89LP51RD2/ED2/ID2 allows for a wide V be sufficient to prevent incorrect execution if V range, such as when a 5.0V supply is coupled with high frequency operation. In such cases an external Brown-out Reset ...
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Hardware Watchdog Reset When the Hardware Watchdog times out, it will generate a reset pulse lasting 49 clock cycles. By default this pulse is also output on the RST pin. The output pulse is either open-drain or open-source as ...
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Power Saving Modes The AT89LP51RD2/ED2/ID2 supports two different software selectable power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register. Additional steps may be required to achieve the lowest possible power consumption while using these modes. ...
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Power-down Mode Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops the oscillator, disables the BOD and powers down the Flash memory in order to minimize power consumption. Only the power-on circuitry will continue to ...
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Figure 8-2. PWD XTAL1 INT1 Internal Clock 8.2.2 Reset Recovery from Power-down The wake-up from Power-down through an external reset is similar to the interrupt with PWDEX = “1”. At the rising edge of RST, Power-down is exited, the oscillator ...
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Low Power Configuration Several of the nonvolatile User Configuration Fuses can enable modes where less power will be consumed during normal operation as listed in once by an external programmer to match the desired operating environment. Table 8-2. Fuse ...
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Interrupts The AT89LP51RD2/ED2/ID2 provides 11 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1 and 2), a serial port interrupt, an SPI interrupt, a key- board interrupt, a PCA interrupt, an analog comparator interrupt ...
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Table 9-2. Figure 9-1. INT0 INT1 PCA IT EXF2 KBD IT TWIF SPIF TXE MODF CFA CFB ADIF AT89LP51RD2/ED2/ID2 Preliminary 62 Priority Level Bit Values IPH Interrupt Control Subsystem IEN1, IEN0 IT0 EX0 IE0 ET0 TF0 ...
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Interrupt Response The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls the flags in the last clock cycle of the instruction in progress. If one of the flags was set in ...
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Figure 9-2. Minimum Interrupt Response Time (Fast Mode) Clock Cycles 1 INT0 IE0 Ack. Instruction Cur. Instr. Figure 9-3. Maximum Interrupt Response Time (Fast Mode) Clock Cycles 1 INT0 IE0 Instruction RETI Figure 9-4. Minimum Interrupt Response Time (Compatibility Mode) ...
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Interrupt Registers Table 9-3. IEN0 – Interrupt Enable Register 0 IEN0 = A8H Bit Addressable EA EC Bit 7 6 Symbol Function Global Interrupt Enable EA All interrupts are disabled when When each ...
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Table 9-5. IPL0 – Interrupt Priority Low Register 0 IPL0 = B8H Bit Addressable IP0DIS PPCL Bit 7 6 Symbol Function Interrupt Level 0 Disable IP0DIS Clear to enable all interrupts with priority level 0. Set to disable all interrupts ...
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Table 9-7. IPH0 – Interrupt Priority High Register 0 IPH0 = B7H Not Bit Addressable IP1DIS PPCH Bit 7 6 Symbol Function Interrupt Level 1 Disable IP1DIS Clear to enable all interrupts with priority level 1. Set to disable all ...
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External Interrupts The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP51RD2/ED2/ID2 may be used as external interrupt sources. The external interrupts can be programmed to be level-activated or transition- activated by setting or clearing bit IT1 or IT0 ...
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Figure 11-1. Keyboard Block Diagram KBLS 1 (P1.7) GPI7 0 1 (P1.6) GPI6 0 1 (P1.5) GPI5 0 1 (P1.4) GPI4 0 1 (P1.3) GPI3 0 1 (P1.2) GPI2 0 1 (P1.1) GPI1 0 1 (P1.0) GPI0 0 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 ...
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Registers . Table 11-1. – Keyboard Mode Register KBMOD KBMOD = 9FH Not Bit Addressable KBMOD7 KBMOD6 Bit 7 6 KBMOD level-sensitive interrupt for P1 edge-triggered interrupt for P1.x Table 11-2. – Keyboard Level Select ...
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I/O Ports The AT89LP51RD2/ED2/ID2 can be configured for between 36 and 40 I/O pins. The exact num- ber of general I/O pins available depends on the clock and external memory configuration as shown in Table 12-1. Clock Source A ...
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Table 12-2. PxM0.y . Table 12-3. Port . Table 12-4. Register P0M0 P0M1 P1M0 P1M1 P2M0 P2M1 P3M0 P3M1 P4M0 P4M0 12.1.1 Quasi-bidirectional Output Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasi- ...
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A second pull-up, called the “weak” pull-up, is turned on when the port latch for the pin contains a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the primary source current for ...
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Open-drain Output The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic “0” used as a logic output, a port con- figured ...
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Digital inputs on P2.4, P2.5, P2.6 and P2.7 are disabled whenever an analog comparator is enabled by setting the CENA or CENB bits in ACSRA and ACSRB and that pin is configured for input-only mode. To use an analog input ...
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Table 12-6. PxM0.y Table 12-7. Port Pin P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 AT89LP51RD2/ED2/ID2 Preliminary 76 Pin Function Configurations for Port x Pin y PxM1 Port ...
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Table 12-7. Port Pin P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 3714A–MICRO–711 AT89LP51RD2/ED2/ID2 Preliminary Port Pin Alternate Functions Configuration Bits PxM0.y PxM1.y P1M0.4 P1M1.4 P1M0.5 P1M1.5 P1M0.6 P1M1.6 ...
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Table 12-7. Port Pin P3.7 P4.0 P4.1 P4.2 P4.4 P4.5 P4.6 P4.7 AT89LP51RD2/ED2/ID2 Preliminary 78 Port Pin Alternate Functions Configuration Bits PxM0.y PxM1.y P3M0.7 P3M1.7 P4M0.0 P4M1.0 P4M0.1 P4M1.1 P4M0.2 P4M1.2 P4M0.4 P4M1.4 P4M0.5 P4M1.5 P4M0.6 P4M1.6 P4M0.7 P4M1.7 Alternate ...
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Enhanced Timer 0 and Timer 1 with PWM The AT89LP51RD2/ED2/ID2 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the fol- lowing features: • Two 16-bit timer/counters with 16-bit reload registers • Two independent 8-bit precision PWM outputs ...
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Registers Table 13-1 Table 13-1. Name TCON TMOD TL0 TL1 TH0 TH1 TCONB RL0 RL1 RH0 RH1 Note: . Table 13-2. – Timer/Counter Control Register TCON TCON = 88H Bit Addressable TF1 TR1 Bit 7 6 Symbol Function Timer ...
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Table 13-3. TMOD – Timer/Counter Mode Control Register TMOD Address = 089H Not Bit Addressable GATE1 C/T1 Bit 7 6 Symbol Function Timer 1 Gating Control GATE1 When set, Timer/Counter 1 is enabled only while INT1 pin is high and ...
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Table 13-4. – Timer/Counter Control Register B TCONB TCONB = 91H Not Bit Addressable PWM1EN PWM0EN Bit 7 6 Symbol Function Pulse Width Modulation 1 Enable PWM1EN Set to configure Timer 1 for Pulse Width Modulation output on T1 (P3.5). ...
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Figure 13-1. Timer/Counter 1 Mode 0: Variable Width Counter GATE1 INT1 Pin 13.3 Mode 1 – 16-bit Auto-Reload Timer/Counter In Mode 1 the Timers are configured for 16-bit auto-reload. The Timer register is run with all 16 bits. The 16-bit ...
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Mode 2 – 8-bit Auto-Reload Timer/Counter Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure TH1, which is preset by software. The reload leaves TH1 unchanged. Mode 2 operation is ...
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Figure 13-4. Timer/Counter 0 Mode 3: Two 8-bit Counters 13.6 Pulse Width Modulation On the AT89LP51RD2/ED2/ID2, Timer 0 and Timer 1 may be independently configured as 8-bit asymmetrical (edge-aligned) pulse width modulators (PWM) by setting the PWM0EN or PWM1EN bits ...
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Mode 0 – 8-bit PWM with 8-bit Logarithmic Prescaler In Mode 0, TLn acts as a logarithmic prescaler driving 8-bit counter THn (see PSCn bits in TCONB control the prescaler value. On THn overflow, the duty cycle value in ...
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Figure 13-7. Timer/Counter 1 PWM Mode 1 GATE1 INT1 Pin 13.6.3 Mode 2 – 8-bit Frequency Generator Timer n in PWM Mode 2 functions as an 8-bit Auto-Reload timer, the same as normal Mode 2, with the exception that the ...
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Figure 13-9. PWM Mode 2 Waveform 13.6.4 Mode 3 – Split 8-bit PWM Timer 1 in PWM Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in PWM Mode 3 establishes ...
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Figure 13-10. Timer/Counter 0 PWM Mode 3 14. Timer 2 The AT89LP51RD2/ED2/ID2 includes a 16-bit Timer/Counter 2 with the following features: • 16-bit timer/counter with one 16-bit reload/capture register • One external reload/capture input • Up/Down counting mode with external ...
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Note: In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre- sponding external input pin, T2. In Fast mode the external input is sampled every clock cycle. When the samples show a high ...
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Timer 2 Registers Control and status bits for Timer 2 are contained in registers T2CON (see T2MOD (see 16-bit timer register for Timer 2. The register pair {RCAP2H, RCAP2L} at addresses 0CBH and 0CAH are the 16-bit Capture/Reload register ...
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Table 14-4. T2MOD – Timer 2 Mode Control Register T2MOD Address = 0C9H Not Bit Addressable – – Bit 7 6 Symbol Function T2OE Timer 2 Output Enable When T2OE = 1 and C/ the T2 pin will ...
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Auto-Reload Mode Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see count up. When ...
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Figure 14-3. Timer 2 Waveform: Auto-Reload Mode (DCEN = 0) 14.3 Down Counter Setting DCEN = 1 enables Timer 2 to count up or down, as shown in the T2EX pin controls the direction of the count (if ...
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Figure 14-5. Timer 2 Diagram: Auto-Reload Mode (DCEN = 1) CLK SYS 14.4 Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON 14-3). Note that the baud rates for transmit ...
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Figure 14-6. Timer 2 in Baud Rate Generator Mode T2EX PI N 14.5 Frequency Generator (Programmable Clock Out) Timer 2 can generate a 50% duty cycle clock on T2 (P1.0). This pin, besides being a regular I/O ...
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Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time ...
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The CMOD register includes three additional bits associated with the PCA (See Table 15-2). • The CIDL bit which allows the PCA to stop during idle mode. • The WDTE bit which enables or disables the watchdog function on module ...
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Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. • ...
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Table 15-5. CL – PCA Counter Register Low CL Address = 0E9H Not Bit Addressable C7 C6 Bit 7 6 Symbol Function Module n Compare/Capture Register Low C 7-0 Holds the lower order bits of the 16-bit PCA Timer/Counter. Figure ...
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The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the modules capture/compare register. • The match bit MAT (CCAPMn.3) when set will ...
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Note: PCA Module Modes (CCAPMn Registers ECOMn CAPPn CAPNn MATn There are two additional registers associated ...
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PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on ...
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High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the modules capture registers as shown in 15-6. To ...
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Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output ...
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PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. ...
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The program sequence to feed or enable the watchdog timer is as follows: Table 16-1. WTO2 The WDT time-out period is dependent on the system clock frequency. 16.1 Software Reset A Software Reset of the AT89LP51RD2/ED2/ID2 is accomplished by writing ...
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WDT Registers ) Table 16-2. WDTPRG – Watchdog Control Register WDTPRG Address = A7H Not Bit Addressable WDTOVF SWRST Bit 7 6 Symbol Function Watchdog Overflow Flag WDTOVF Set by hardware when a WDT rest is generated by the ...
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Serial Interface (UART) The serial interface on the AT89LP51RD2/ED2/ID2 implements a Universal Asynchronous Receiver/Transmitter (UART). The UART has the following features: • Full-duplex Operation • Data Bits • Framing Error Detection • Multiprocessor Communication Mode with ...
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Table 17-1. SCON – Serial Port Control Register SCON Address = 98H Bit Addressable SM0/FE SM1 Bit 7 6 (1) (SMOD0 = 0/1) Symbol Function Framing Error Bit This bit is set by the receiver when an invalid stop bit ...
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Multiprocessor Communications Modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received, followed by a stop bit. The 9th bit goes into RB8. Then comes a stop bit. The port ...
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Table 17-2. TCLK (T2CON. 17.2.1 Using Timer 1 to Generate Baud Rates Setting TB8 = 1 in Mode 0 enables Timer 1 as the baud rate generator. When Timer 1 is ...
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Table 17-3. Commonly Used Baud Rates Generated by Timer 1 Baud Rate f (MHz) OSC Mode 0 Max: 6 MHz 12 Mode 2 Max: 750K 12 Modes 1, 3 Max: 750K 12 19.2K 11.059 9.6K 11.059 4.8K 11.059 2.4K 11.059 ...
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Table 17-4. Baud Rate Max: 750K 19.2K 9.6K 4.8K 2.4K 1.2K 137.5 110 110 19.2K 9.6K 4.8K 2.4K 1.2K 137.5 110 17.2.3 Internal Baud Rate Generator (BRG) The AT89LP51RD2/ED2/ID2 includes an Internal Baud Rate Generator (BRG) for UART modes 1 ...
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Figure 17-1. Internal Baud Rate Generator Table 17-5. Baud Rate 115200 57600 38400 28800 19200 9600 4800 4800 2400 1200 600 Table 17-6. BRL – Baud Rate Reload Register BRL Address = 09AH Not Bit Addressable Bit 7 6 Symbol ...
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Table 17-7. BDRCON – Baud Rate Control Register BDRCON Address = 9BH Not Bit Addressable – – Bit 7 6 Symbol Function Baud Rate Run Control BRR Clear to stop the Internal Baud Rate Generator. Set to start the Internal ...
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Given Address Two special Function Registers are used to define the slave’s address, SADDR (A9H), and the address mask, SADEN (B9H). SADEN is used to define which bits in the SADDR are to be used and which bits are ...
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Broadcast Address The Broadcast Address for each slave is created by taking the logic OR of SADDR and SADEN. Zeros in this result are trended as don’t cares. In most cases, interpreting the don’t cares as ones, the broadcast ...
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Two-Wire (Half-Duplex) Mode Transmission is initiated by any instruction that uses SBUF as a destination register. The “write to SBUF” signal also loads a “1” into the 9th position of the transmit shift register and tells the TX Control ...
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Figure 17-2. Mode 0 Waveforms (Two-Wire) SMOD1 = 0 TXD SM2 = 0 RXD (TX) RXD (RX) SMOD1 = 1 TXD SM2 = 0 RXD (TX) RXD (RX) SMOD1 = 0 TXD SM2 = 1 RXD (TX) RXD (RX) SMOD1 ...
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Figure 17-4. Serial Port Mode 0 (Two-Wire) TIMER 1 O VERF sys 1 0 TB8 ÷2 ÷ SMOD1 WRITE SEND SHIFT RXD ( OUT ...
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More About Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In ...
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Figure 17-5. Serial Port Mode 1 TIMER 1 TIMER 2 OVERFLOW OVERFLOW WRITE ÷2 TO SBUF “0” “1” SMOD1 “0” “1” TCLK “0” “1” INTERRUPT RCLK SAMPLE 1-TO-0 TRANSITION DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 ...
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More About Modes 2 and 3 Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th ...
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Figure 17-6. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 3714A–MICRO–7/11 AT89LP51RD2/ED2/ID2 Preliminary INTERNAL BUS INTERNAL BUS 125 ...
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Figure 17-7. Serial Port Mode 3 TIMER 1 TIMER 2 OVERFLOW OVERFLOW WRITE TO ÷2 SBUF “0” “1” SMOD1 “0” “1” TCLK “0” “1” INTERRUPT RCLK SAMPLE 1-TO-0 TRANSITION DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 ...
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Enhanced Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed, full-duplex synchronous data transfer between the AT89LP51RD2/ED2/ID2 and peripheral devices or between multiple microcon- troller devices, including multiple masters and slaves on a single bus. The SPI includes ...
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Interface Description The interconnection between master and slave devices with SPI is shown in pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Serial Clock (SCK), and Slave Select (SS). The MSTR bit in SPCON determines the directions of ...
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Master Output / Slave Input (MOSI) This 1-bit signal is directly connected between the master device and all slave devices. The MOSI line is used to transfer data in series from the master to the slave. Therefore ...
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If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with SSIG = 0, the SPI system interprets this as another master selecting the SPI as a slave and starting to send ...
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Master Operation An SPI master device initiates all data transfers on the SPI bus. The AT89LP51RD2/ED2/ID2 is configured for master operation by setting MSTR = 1 in SPCON. Writing to the SPI data register (SPDAT) while in master mode ...
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MISO in response to the serial clock on SCK. While SS is high, the SPI slave will remain sleeping with MISO inactive. Three-wire mode is enabled by setting SSIG = 1. In this mode SS is ...
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SS Error Flag (SSERR) A Synchronous Serial Slave Error occurs when SS goes high before the end of a received data in slave mode. SSERR does not cause in interruption, this bit is cleared by writing 0 to SPEN ...
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Registers Table 18-3. SPCON – SPI Control Register SPCON Address = C3H Not Bit Addressable SPR2 SPEN Bit 7 6 Symbol Function Serial Peripheral Clock Rate 2 SPR2 See the description for SPR Serial peripheral Enable SPEN SPI = ...
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Table 18-4. SPDAT – SPI Data Register SPDAT Address = C5H Not Bit Addressable SPD7 SPD6 Bit 7 6 Table 18-5. SPSTA – SPI Status Register SPSTA Address = C4H Not Bit Addressable SPIF WCOL Bit 7 6 Symbol Function ...
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... AT89LP51RD2/ED2/ID2 Preliminary 136 Figure 19-1 The TWI is available on both the AT89LP51RD2 and AT89LP51ED2 where as it was not available on the AT89C51RD2 and AT89C51ED2. The TWI is not available in the PDIP package. Device 1 Device 3 Device 2 ...
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Data Transfer and Frame Format 19.1.1 Transferring Bits Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is ...
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SDA line should be left high in the ACK clock cycle. The Master can then transmit a STOP condition REPEATED START condition to initiate a new transmission. An address packet consisting of a slave address ...
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Combining Address and Data Packets Into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condi- ...
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Figure 19-7. SCL Synchronization between Multiple Masters SCL from Master A SCL from Master B SCL bus Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line ...
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It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composi- tion of SLA+R/W and data packets. In other words: All transmissions ...
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Table 19-1. CR2 19.3.3 Bus Interface Unit This unit contains the Data and Address Shift Register (SSDAT), a START/STOP Controller and Arbitration detection hardware. The SSDAT contains the address or data bytes ...
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After the TWI has transmitted a START/REPEATED START condition. • After the TWI has transmitted SLA+R/W. • After the TWI has transmitted an address byte. • After the TWI has lost arbitration. • After the TWI has been addressed ...
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Table 19-3. SSCS – Two-Wire Status Register SSCS Address = ABH Not Bit Addressable SC7 SC6 Bit 7 6 Symbol Function Two-wire Interface Status The current status code of the TWI logic and serial bus. See SC 7-0 status codes. ...
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If the TWE bit is cleared, the application must poll the SI flag in order to detect actions on the TWI bus. When the SI flag is asserted, the TWI has finished an operation and awaits application response. ...
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When the address packet has been transmitted, the SI flag in SSCON is set, and SSCS is updated with a status code indicating that the address packet has successfully been sent. The status code will also reflect whether a ...
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S: START condition Rs: REPEATED START condition R: Read bit (high level at SDA) W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte ...
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SSCON Value A REPEATED START condition is generated by writing the following value to SSCON: SSCON Value After a repeated START condition (status 10h) the Two-wire Serial Interface can access the same slave again new slave without transmitting ...
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Table 19-6. Status Codes for Master Transmitter Mode Data byte has been 30h transmitted; NOT ACK has been received Arbitration lost in SLA+W 38h or data bytes 19.6.2 Master Receiver Mode In the Master Receiver mode, a number of data ...
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Figure 19-11. Format and States in Master Transmitter Mode Successfull S SLA transmission to a slave receiver 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte ...
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Table 19-7. Status Codes for Master Receiver Mode Status Status of the Two-wire Code Serial Bus and Two-wire (SSCS) Serial Interface Hardware A START condition has 08h been transmitted A repeated START 10h condition has been transmitted Arbitration lost in ...
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Figure 19-12. Format and States in Master Receiver Mode Successfull S SLA reception from a slave receiver 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data ...
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SSIE must be written to one to enable the TWI. The AA bit must be written to one to enable the acknowledgment of the device’s own slave address or the general call address. STA and STO must be written to ...
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Table 19-8. Status Codes for Slave Receiver Mode Previously addressed with own SLA+W; data has been 88h received; NOT ACK has been returned Previously addressed with general call; data has been 90h received; ACK has been returned Previously addressed with ...
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Figure 19-13. Format and States in Slave Receiver Mode Reception of the own S slave address and one or more data bytes. All are acknowledged Last data byte received is not acknowledged Arbitration lost as master and addressed as slave ...
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Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver. To initiate the Slave Transmitter mode, upper 7 bits of SSADR must be initialized with the address to which the ...
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Table 19-9. Status Codes for Slave Transmitter Mode Status Status of the Two-wire Code Serial Bus and Two-wire (SSCS) Serial Interface Hardware Own SLA+R has been A8h received; ACK has been returned Arbitration lost in SLA+R/W as master; own ...
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Examples of such illegal positions are during the serial transfer of an address byte, a data byte acknowledge bit. When a bus error occurs set. To recover from a bus error, the STO flag must set ...
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Dual Analog Comparators The AT89LP51RD2/ED2/ID2 provides two analog comparators. The analog comparators have the following features: • Internal 3-level Voltage Reference (1.125V, 1.25V, 1.375V) • Four Shared Analog Input Channels – Configure as Multiple Input Window Comparator • Selectable ...
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Each comparator may be configured to cause an interrupt under a variety of output value condi- tions by setting the CMx interrupt flags CFx in ACSRx are set whenever the comparator outputs match the conditions specified by CMx rupt and ...
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Internal Reference Voltage The negative input terminal of each comparator may be connected to an internal voltage refer- ence by changing the RFB set to 1.25 V ±5%. The voltage reference also provides two additional voltage levels approxi- mately ...
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Figure 20-4. Dual Comparator Configuration Examples a. dual independent comparators with external references + AIN0 A - AIN1 CSA = 00 RFA = 00 b. 3-channel comparator with external reference AIN0 AIN2 AIN1 AIN3 CSA = 00/10/11 RFA = 00 ...
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Table 20-1. – Analog Comparator A Control & Status Register ACSRA ACSRA = A3H Not Bit Addressable CSA1 CSA0 Bit 7 6 Symbol Function CSA Comparator A Positive Input Channel Select 1-0 CSA1 CSA0 ...
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Table 20-2. – Analog Comparator B Control & Status Register ACSRB ACSRB = ABH Not Bit Addressable CSB1 CSB0 Bit 7 6 Symbol Function CSB Comparator B Positive Input Channel Select 1-0 CSB1 CSB0 B+ Channel 0 0 AIN0 (P2.4) ...
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Table 20-3. – Analog Comparator Reference Control Register AREF AREF = BDH Not Bit Addressable CMPB CMPA Bit 7 6 Symbol Function CMPB Comparator B Output. Copy of Comparator B raw output value sampled by the system clock. CMPA Comparator ...
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Digital-to-Analog/Analog-to-Digital Converter The AT89LP51RD2/ED2/ID2 includes a 10-bit Data Converter (DADC) with the following features: • Digital-to-Analog (DAC) or Analog-to-Digital (ADC) Mode • 10-bit Resolution • 6.5 µs Conversion Time • 7 Multiplexed Single-ended Channels or 3 Differential Channels • ...
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To convert the unsigned binary value back to 2’s complement, subtract 02h from DADH in right- adjusted mode or 80h from DADH in left-adjusted mode. Note that the DADH/DADL registers cannot be directly manipulated as they are read-only in ADC ...
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Table 21-1. Right Adjust 0 0100h 01FFh FF00h FE01h 21.1 ADC Operation The ADC converts an analog input voltage to a 10-bit signed digital value through successive approximation. When DIFF (DADI.3) is zero, the ADC operates in single-ended mode and ...
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A timing diagram of an ADC conversion is shown in ADC clock cycles to complete. The analog input is sampled during the third cycle of the conver- sion and is held constant for the remainder of the conversion. At the ...
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DIFF, ACON and ACS bits have no effect in DAC mode. P2.2 and P2.3 are automatically forced to input-only mode while the DAC is enabled. A timing diagram of a DAC conversion is shown in clock ...
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In ADC mode, there are no requirements on the clock frequency with respect to the system clock. The ADC prescaler selection is independent of the system clock divider and the ADC may operate at both higher or lower frequencies than ...
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Registers Table 21-2. – DADC Control Register DADC DADC = A4H Not Bit Addressable ADIF GO/BSY Bit 7 6 Symbol Function ADIF ADC Interrupt Flag Set by hardware when a conversion completes. Cleared by hardware when calling the interrupt ...
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Symbol Function ACON Analog Input Connect When cleared, the analog inputs are disconnected from the ADC. When set, the analog inputs selected by ACS connected to the ADC. ACON must be zero when changing the input channel multiplexor (ACS IREF ...
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Note: When LADJ = 0, bits 7–0 of the ADC result are found in bits 7–0 of DADL. When LADJ = 1, bits 1–0 of the ADC result are found in bits 7–6 of DADL. Bits 5–0 are cleared to ...
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Instruction Set Summary The AT89LP51RD2/ED2/ID2 is fully binary compatible with the 8051 instruction set. In Compati- bility mode the AT89LP51RD2/ED2/ID2 has identical execution time with AT89C51RD2/ED2 and other standard 8051s. The difference between the AT89LP51RD2/ED2/ID2 in Fast mode and ...
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Table 22-1. DEC Rn DEC direct DEC @Ri DEC A INC DPTR INC /DPTR MUL AB DIV MAC AB (2) CLR M (2) ASR M (2) LSL M Logical CLR A CPL A ANL A, Rn ANL ...
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Table 22-1. SWAP A Data Transfer MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV ...
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Table 22-1. SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C Branching JC rel JNC rel JB bit, rel JNB bit, rel JBC ...
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Instruction Set Extensions The following instructions are extensions to the standard 8051 instruction set that provide enhanced capabilities not found in standard 8051 devices. All extended instructions start with an A5H escape code. For this reason random A5H reserved ...
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CJNE rel i Function: Compare and Jump if Not Equal Description: CJNE compares the magnitudes of the Accumulator and indirect RAM location and branches if their values are not equal. The branch destination is computed by ...
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INC /DPTR Function: Increment Alternate Data Pointer Description: INC /DPTR increments the unselected 16-bit data pointer 16-bit increment (modulo 2 and an overflow of the low-order byte of the data pointer from 0FFH to 00H increments ...
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LSL M Function: Shift MAC Accumulator Left Logically Description: The forty bits in the M register are shifted one bit to the left. Bit 0 is cleared. No flags are affected. Example: The M register holds the value 0C5B1A29384H. ...
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MAC AB Function: Multiply and Accumulate Description: MAC AB multiplies the signed 16-bit integers in the register pairs {AX, A} and {BX, B} and adds the 32-bit product to the 40-bit M register. The low-order bytes of the 16-bit ...
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MOVX A, @/DPTR Function: Move External using Alternate Data Pointer Description: The MOVX instruction transfers data from external data memory to the Accumulator. The unselected Data Pointer generates a 16-bit address which targets EDATA, FDATA or XDATA. Example: DPS ...
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On-Chip Debug System The AT89LP51RD2/ED2/ID2 On-Chip Debug (OCD) System uses a two-wire serial interface to control program flow; read, modify, and write the system state; and program the nonvolatile memory. The OCD System has the following features: • Complete ...
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Software Breakpoints The AT89LP51RD2/ED2/ID2 microcontroller includes a BREAK instruction for implementing program memory breakpoints in software. A software breakpoint can be inserted manually by placing the BREAK instruction in the program code. Some emulator systems may allow for auto- ...
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... CPU to be operational, i.e. no clock is required except the SPI serial clock. This interface can be used both in-system and in a stand-alone programmer, and has full access to all nonvolatile memory resources. This interface is compatible with the Atmel AT89LP ISP Studio software. See for more information. • ...
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... The AT89LP51RD2/ED2/ID2 offers 64K bytes of In-System Programmable nonvolatile Flash code memory and 4K bytes of nonvolatile EEPROM data memory. In addition, the device con- tains a 512-byte User Signature Array, a 128-byte read-only Atmel Signature Array and 19 User Configuration Fuses. The memory organization is shown in code memory and auxiliary memories are divided into pages of 128 bytes each and share a tem- porary page buffer of 64 bytes (one half page) ...
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... The Oscillator Calibration Byte controls the frequency of the internal RC oscillator. The fre- quency is inversely proportional to the calibration value such that higher values result in lower frequencies. A copy of the factory-set calibration value is stored at location 0008H of the Atmel Signature. User Signature ISP Programming Behavior ...
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... The Device ID values are shown in byte is also stored at address 0008H. Table 24-4. Device AT89LP51RD2 AT89LP51ED2 AT89LP51ID2 24.2 User Configuration Fuses The AT89LP51RD2/ED2/ID2 includes 19 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row, with each byte representing one fuse as listed in code bytes except they are not affected by Chip Erase ...
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... Lock bit mode Lock bit mode 3 implements mode 2 and also blocks reads from the code and data memories; however, reads of the User Signature Array, Atmel Signature Array, and User Configuration Fuses are still allowed. The Hardware Security bits only restrict the access of the SPI-based ISP interface. The Hard- ware Security Bits will not disable the Bootloader or any programming initiated by the application software using IAP ...
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... IAP. These Flash API are also executed by the bootloader. To call the corresponding API, the user may use a set of routines which can be linked with the application. Example of Flash_api routines are available on the Atmel web site on the software application note: C Flash Drivers for the AT89C51RD2/ED2 The API calls description and arguments are shown in The application selects an API by setting R1, ACC, DPTR0 and DPTR1 registers ...
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Table 24-7. API Call Summary Command R1 READ MANUF ID 00h XXh READ DEVICE ID1 00h XXh READ DEVICE ID2 00h XXh READ DEVICE ID3 00h XXh ERASE BLOCK 01h XXh PROGRAM DATA Value to 02h BYTE write PROGRAM SSB ...
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... Setting FPS takes precedence over the EXTRAM bit in AUXR. The other memory spaces (User and Atmel Signatures, User Fuses, Hardware Security) are made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON regis- ter in accordance with spaces ...
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... Interrupts that may occur during programming time must be disabled to avoid any spurious exit of the programming mode. Addressable space User Application (0000–FFFFH) User Signature (0000–01FFH) Atmel Signature (0200–027FH read-only) User Fuses (0000–007FH) Hardware Security Bits (0080–00FFH read-only) Reserved Table 24-9 ...
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Figure 24-2. Page Programming Structure Any number of data bytes from can be loaded into the temporary page buffer. This pro- vides the capability to program the whole memory by byte, by half-page or by any number ...
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Figure 24-3. Flash Page Buffer Loading Procedure Note: 24.4.2.6 Programming the User Signature Space The following procedure is used to program the User Signature space and is summarized in ure 24-4: 1. Load up to one half-page of data in ...
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Figure 24-4. Flash Programming Procedure 24.4.2.7 Programming the User Fuse Space The following procedure is used to program the User Fuse space and is summarized in 24-4: 1. Load up to one half-page of data in the page buffer from ...
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... Reading the User/Atmel Signature The following procedure is used to read the User or Atmel Signature space and is summarized in Figure • Map the Signature space by writing 02H to FCON register • Read one byte in Accumulator by executing MOVC A,@A+DPTR where A+DPTR is 0000– 01FFH for the User Signature and 0200–027FH for the Atmel Signature • ...
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... FPL1 FPL0 FPS Memory Operation Target 0 CODE space (0000–FFFFH) User Signature space (0000–01FFH) 1 Atmel Signature space (0200–027FH read-only) User Fuse space (0000–007FH) 0 Hardware Security space (0080–00FFH read-only) 1 Reserved Reset Value = xxxx 000xB FMOD1 FMOD0 FBUSY 2 ...