W9751G6JB-25 Winbond Electronics, W9751G6JB-25 Datasheet
W9751G6JB-25
Specifications of W9751G6JB-25
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W9751G6JB-25 Summary of contents
Page 1
... Self Refresh Entry Command ..........................................................................................21 7.3.8 Self Refresh Exit Command .............................................................................................22 7.3.9 Refresh Command ...........................................................................................................22 7.3.10 No-Operation Command ..................................................................................................23 7.3.11 Device Deselect Command..............................................................................................23 7.4 Read and Write access modes ...........................................................................................................23 7.4.1 Posted CAS 7.4.1.1 Examples of posted ....................................................................................................................23 operation......................................................................23 CAS - 1 - W9751G6JB Publication Release Date: Aug. 03, 2010 Revision A04 ...
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... Differential Input/Output AC Logic Levels ...........................................................................................65 9.14 AC Overshoot / Undershoot Specification ...........................................................................................66 9.14.1 AC Overshoot / Undershoot Specification for Address and Control Pins: ........................66 9.14.2 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins:..........66 10. TIMING WAVEFORMS .......................................................................................................................67 10.1 Command Input Timing.......................................................................................................................67 W9751G6JB Publication Release Date: Aug. 03, 2010 - 2 - Revision A04 ...
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... Active Power Down Mode Entry and Exit Timing.......................................................................83 10.31 Precharged Power Down Mode Entry and Exit Timing ..............................................................83 10.32 Clock frequency change in precharge Power Down mode ........................................................84 11. PACKAGE SPECIFICATION ..............................................................................................................85 Package Outline WBGA-84 (8x12.5 mm 12. REVISION HISTORY ..........................................................................................................................86 2 ).......................................................................................................85 Publication Release Date: Aug. 03, 2010 - 3 - W9751G6JB Revision A04 ...
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... GENERAL DESCRIPTION The W9751G6JB is a 512M bits DDR2 SDRAM, organized as 8,388,608 words × 4 banks × 16 bits. This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for general applications. W9751G6JB is sorted into the following speed grades: -18, -25, 25I and -3. The -18 is compliant to the DDR2-1066 (7-7-7) specification. The -25/25I are compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade which is guaranteed to support -40° ...
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... Min. 13.125 nS Min. 53.125 nS Min. Max. 105 mA Max. 115mA Max. 165 mA Max. 200 mA Max. 105 mA ≦ 85°C) Max. Max. 245 mA Publication Release Date: Aug. 03, 2010 - 5 - W9751G6JB DDR2-800 DDR2-667 5-5-5/6-6-6 5-5-5 -18 -25/25I -3 − − − − 7.5 nS − 2.5 nS 2.5 nS − ...
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... VDDQ D DQ10 E VSSQ LDQS F LDQS G VDDQ H DQ2 J VSSDL K RAS L CAS A11 R NC Publication Release Date: Aug. 03, 2010 - 6 - W9751G6JB 8 9 UDQS VDDQ VSSQ DQ15 DQ8 VDDQ VSSQ DQ13 VDDQ VSSQ DQ7 DQ0 VDDQ VSSQ DQ5 CLK VDD CLK ODT CS A0 VDD A4 A8 ...
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... DQ Power Supply: 1.8V ± 0.1V. DQ Power Supply DQ Ground DQ Ground. Isolated on the device for improved noise immunity. No Connection No connection. DLL Ground DLL Ground. DLL Power Supply: 1.8V ± 0.1V. DLL Power Supply - 7 - W9751G6JB DESCRIPTION are masked when CS is Publication Release Date: Aug. 03, 2010 Revision A04 registered ...
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... CELL ARRAY BANK #0 SENSE AMPLIFIER SENSE AMPLIFIER PREFETCH REGISTER DATA CONTROL CIRCUIT COLUMN DECODER COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER SENSE AMPLIFIER Publication Release Date: Aug. 03, 2010 - 8 - W9751G6JB CELL ARRAY BANK #1 ODT DQ0 | DQ DQ15 ODT BUFFER LDQS LDQS CONTROL UDQS UDQS ...
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... The DDR2 SDRAM is now ready for normal operation. DDQ voltage ramp are driven from a single power converter output DDQ W9751G6JB *1 and ODT at a LOW state (all other ramps from 300 DD | ≦ 0.3 volts. DDQ during voltage ramp time to avoid DDQ ≧ V ≧ ...
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... DD min is achieved when PRE MRS REF REF ALL MRD RP RFC MRD DLL min 200 Cycle Reset - 10 - W9751G6JB ramps from 300 min. DD min is achieved on V must be no DDQ DDQ t IS ANY MRS EMRS EMRS CMD RFC MRD Follow OCD OIT Flow chart ...
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... ODT setting. A10 DLL TM CAS Latency A7 Mode 0 Normal 1 Test Write recovery for Auto-precharge A11 A10 Reserved Figure 2 – Mode Register Set (MRS W9751G6JB Address Field BT Burst Length Mode Register Burst Length A3 Burst Type Sequential Interleave CAS Latency Latency Reserved Reserved Reserved ...
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... Output Driver Impedance Control Strobe Function Matrix Output driver A1 impedance control DQS DQS 0 DQS DQS DQS Hi-z 1 Reduced Figure 3 – EMR ( W9751G6JB Address Field BT Rtt D.I.C DLL Extended Mode Register (1) A0 DLL Enable 0 Enable 1 Disable Additive Latency A4 A3 Latency ...
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... When DRAM is operated at 85 °C < TCASE ≤ 95 °C the extended Self Refresh rate must be enabled by setting bit A7 to "1" before the Self Refresh mode can be entered SELF A7 High Temperature Self Refresh Rate Enable 0 Disable 1 Enable* Figure 4 – EMR ( W9751G6JB ) must be satisfied to MRD Address Field 1 0* Extended Mode Register (2) 2 Publication Release Date: Aug. 03, 2010 Revision A04 ...
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... EMR (3) must be programmed during initialization for proper operation Note: 1. All bits in EMR (3) except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR (3 Figure 5 – EMR (3) Publication Release Date: Aug. 03, 2010 - 14 - W9751G6JB Revision A04 ...
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... ALL OK EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End Publication Release Date: Aug. 03, 2010 - 15 - W9751G6JB EMRS: Drive(0) DQ &DQS Low; DQS High Test Need Calibration EMRS: Enter Adjust Mode BL=4 code input to all DQs ...
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... NOP 1 Increase by 1 step 0 Decrease by 1 step 1 Increase by 1 step 0 Decrease by 1 step - 16 - W9751G6JB at bit time 1, and so forth. The driver Operation Pull-down driver strength NOP (No operation) NOP NOP Increase by 1 step Decrease by 1 step Increase by 1 step Increase by 1 step Decrease by 1 step ...
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... Figure 8. NOP NOP EMRS t OIT DQs high for Drive (1) DQs low for Drive (0) OCD calibration mode exit Figure 8 – OCD Drive Mode - 17 - W9751G6JB /t should be met fixed order and is not affected T3 NOP NOP NOP EMRS ...
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... Rval1 Rval2 Rval3 Input Pin Rval1 Rval2 Rval3 sw2 sw1 sw3 SSQ SSQ SSQ MOD window for proper operation. The timings are shown MOD Publication Release Date: Aug. 03, 2010 - 18 - W9751G6JB ,min and t ,max, and CKE MOD Revision A04 ...
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... Figure 11 – ODT update delay timing - t NOP NOP NOP t MOD,max Updating MOD window, until t MOD EMRS NOP NOP t MOD,max , as measured from outside MOD Publication Release Date: Aug. 03, 2010 - 19 - W9751G6JB NOP NOP t IS New setting ,max is met. MOD NOP NOP NOP AOND New setting Revision A04 ...
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... READ burst; if Auto-precharge is not selected, the row will remain open for subsequent accesses. RAS ). The minimum time interval between Bank Activate RCD RP Publication Release Date: Aug. 03, 2010 - 20 - W9751G6JB and t , respectively. The RRD CCD Revision A04 ...
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... Self Refresh entry is registered; however, the clock must be restarted and stable before the device can exit self refresh operation. min) and t (min) are satisfied. RAS( RTP Publication Release Date: Aug. 03, 2010 - 21 - W9751G6JB Revision A04 ...
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... CKE ≥ NOP CMD Precharge . XSRD t . REFI (max.) . REFI ≥ t RFC NOP REF REF Figure 13 – Refresh command - 22 - W9751G6JB for proper operation XSRD ). NOP or Deselect RFC ≥ t RFC ANY NOP Publication Release Date: Aug. 03, 2010 Revision A04 XSNR . XSNR ). RFC ...
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... Chapter 10) 7.4.1.1 Examples of posted Examples of a read followed by a write to the same bank where and where are shown in Figures 14 and 15, respectively. operation CAS - 23 - W9751G6JB * . The page , and is a minimum of 2 clocks for CCD RCDmin Publication Release Date: Aug. 03, 2010 Revision A04 ...
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... Burst read and write interrupt timing diagram in Chapter 10 Write A-Bank CL=3 RL=AL+CL=5 Dout0 Dout1 Dout2 Dout3 AL=0 Read A-Bank CL=3 RL=AL+CL=3 Dout0 Dout1 Dout2 Dout3 - 24 - W9751G6JB WL=RL-1=4 Din0 Din1 Din2 Din3 Write A-Bank WL=RL-1=2 Din0 Din1 Din2 Din3 Publication Release Date: Aug. 03, 2010 ...
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... The time from the completion of the burst write to bank precharge is the write recovery time (WR). (Example timing waveforms refer to 10.9 and 10.10 Data input (write) timing and Burst write operation diagram in Chapter 10) Sequential Addressing Interleave Addressing (decimal Publication Release Date: Aug. 03, 2010 - 25 - W9751G6JB (decimal Revision A04 ...
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... Minimum Write to Precharge timing BL clock after the un-interrupted burst end and not from the end of the actual burst end. (Example timing waveforms refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in Chapter 10) W9751G6JB , where Publication Release Date: Aug. 03, 2010 ...
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... BA1 BA0 LOW LOW LOW HIGH HIGH LOW HIGH HIGH Don’t Care Don’t Care is satisfied. RAS - 27 - W9751G6JB Precharge Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only All Banks ). A precharge referenced WR Publication Release Date: Aug. 03, 2010 Revision A04 ...
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... Auto-precharge RP ) from the previous bank activation has been satisfied. Limit) and (t Limit) diagram in Chapter 10 has been satisfied from the previous bank activation has been satisfied W9751G6JB (min) are satisfied. (Example timing ends (not at the RTP + (Example timing RP CK(avg ...
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... Minimum Delay between “From Command” to “To Command” BL/2 + max(RTP BL/2 + max(RTP BL/2 + max(RTP BL/2 + max(RTP RFC Publication Release Date: Aug. 03, 2010 - 29 - W9751G6JB Unit Notes clks 1, 2 clks 1, 2 clks 1, 2 clks 1, 2 clks 2 WR clks 2 WR clks ...
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... Clock frequency change in precharge Power Down mode diagram in Chapter 10) has been satisfied. Maximum power down duration is limited by CKE has been satisfied. A valid, executable CKE , t XP XARD - 30 - W9751G6JB if maximum posting of tREFI , after CKE goes HIGH. XARDS Publication Release Date: Aug. 03, 2010 Revision A04 ...
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... The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the refresh requirements outlined in section 7.9. BA1 A12 A10 A9-A0 BA0 A11 BA Row Address Column L Column BA Column H Column BA Column L Column BA Column H Column BA OP Code Publication Release Date: Aug. 03, 2010 - 31 - W9751G6JB NOTES CS RAS CAS 1 1 1,2 1,2 1,2 1,2 1 1,4 ...
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... Refer to the Command Truth Table (200 clocks) is satisfied. XSRD + )” in Self Refresh and Power Down. However ODT must be driven REF W9751G6JB 3 ACTION (N) NOTES Maintain Power Down 11, 13, 15 Power Down Exit 4, 8, 11, 13 Maintain Power Down 11, 15, 16 Self Refresh Exit Active Power Down 4, 8, 10, 11, Entry ...
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... BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 33 - W9751G6JB ACTION NOTES NOP or Power down NOP or Power down ILLEGAL ILLEGAL Row activating Precharge/ Precharge all banks Auto Refresh or Self Refresh Mode/Extended register accessing NOP NOP Begin read Begin write ...
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... BA, CA, A10 READ/READA BA, CA, A10 WRIT/WRITA L H BA, RA ACT L BA, A10 PRE/PREA X AREF/SELF H L Op-Code MRS/EMRS - 34 - W9751G6JB ACTION NOTES Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> ...
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... READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE/PREA H X AREF/SELF L Op-Code MRS/EMRS - 35 - W9751G6JB ACTION NOTES NOP-> Bank active after t WR NOP-> Bank active after t WR ILLEGAL New write ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Precharge after t WR NOP-> Precharge after t WR ...
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... WRITA Writing Reading with with Auto-precharge PRE, PREA PRE, PREA PRE, PREA Precharging - 36 - W9751G6JB CKEL Refreshing CKEL CKEL Autoomatic Sequence Command Sequence Read CKEL = CKE LOW, enter Power Down CKEH = CKE HIGH, exit Power Down CKEH = CKE HIGH, exit Self Refresh ...
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... V 0 DDQ V - 0.04 V REF REF of the transmitting device and V is expected to track variations in V REF (dc). REF of receiving device. REF . AC parameters are measured with W9751G6JB RATING UNIT NOTES -1.0 ~ 2.3 V -0.5 ~ 2.3 V -0.5 ~ 2.3 V -0.5 ~ 2.3 V °C -55 ~ 100 RATING UNIT NOTES ° ° ...
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... IL(ac) IHac (( – 100% Δ DDQ MIN 0.125 REF -0.3 -18 MIN. MAX 0.200 − REF − 0.200 REF W9751G6JB NOM. MAX. UNIT NOTES 75 90 Ω 150 180 Ω Ω and I(V IH (ac) – I(V ) ILac) MAX 0.3 DDQ V - 0.125 REF -25/25I/-3 MIN ...
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... TT − -13.4 13 )/I must be less than 21 Ω for values of V DDQ OH /I must be less than 21 Ω for values max minus a noise margin are delivered to an SSTL_18 receiver W9751G6JB MIN. MAX. UNIT 1.0 2.0 pF − 0.25 pF 1.0 2.0 pF − 0.25 pF 2.5 3 ...
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... MAX RAS RASmin(IDD) 105 , RAS RASmin(IDD) RCD 115 8 ≦ 85 ° C) CASE 50 40 Fast PDN Exit 15 MRS(12 Slow PDN Exit 12 MRS(12 RP(IDD) 75 Publication Release Date: Aug. 03, 2010 - 40 - W9751G6JB -25/25I -3 UNIT NOTES MAX. MAX. 1,2,3,4, 1,2,3,4,5, 100 1,2,3,4, 6,7 1,2,3,4, 1,2,3,4, 1,2,3,4,5, 15 ...
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... C) CASE = 0mA; OUT - RCD(IDD) CK(IDD RRD RRD(IDD) RCD 245 0.1V. /2 limits increase), when T DD CASE must be derated DD6 - 41 - W9751G6JB 1,2,3,4,5, 140 125 mA 1,2,3,4,5, 165 150 mA 1,2,3,4, 1,2,3,4, 1,2,3,4,5, 200 180 mA ≧ 85°C I must be derated DD2P will increase by this amount if T ...
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... CK(IDD) t 13.125 RCD(IDD) t 13.125 RP(IDD) t 53.125 RC(IDD) t RASmin(IDD) t 70000 RASmax(IDD) t RRD(IDD)-2KB t FAW(IDD)-2KB t 105 RFC(IDD) DDR2-800 (-25/25I) 5-5-5/6-6-6 7 5/6 2.5 12.5 12.5 52 70000 105 - 42 - W9751G6JB DDR2-667 (-3) UNIT 5-5-5 5 tCK 70000 105 nS Publication Release Date: Aug. 03, 2010 Revision A04 ...
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... CL=6 2.5 CK(avg CL=7 1.875 CK(avg) 0.48 0.48 -350 -325 7.5 7.5 125 200 325 325 0.6 -0.25 0.2 0.2 0.35 0. W9751G6JB DDR2-1066 (-18) 25 UNIT NOTES 7-7-7 MAX. − nS − nS − nS 70000 nS − nS − 7.8 μS − 3.9 μS − 7.5 ...
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... AC,min Min. (t CH(abs) t CL(abs) − QHS RFC 200 AC,min t AC,min + 2 2.5 t AC,min t AC,min + CK(avg W9751G6JB 25 UNITS NOTES 7-7-7 MAX. − t CK(avg) 0 CK(avg) 1.1 t 14,36 CK(avg) 0.6 t 14,37 CK(avg) 16,27,29, − pS 41,42,44 17,27,29, − pS 41,42,44 16,27,29, − pS 41,42,44 17,27,29, − pS 41,42,44 − ...
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... RP − 7.5 7.5 − − 175 − 250 375 − 375 − − 0.6 -0.25 0.25 − 0.2 − 0.2 0.35 − − 0. W9751G6JB DDR2-667 (-3) 25 UNITS NOTES 5-5-5 MIN. MAX. − − nS − 70000 nS − 105 nS − 7.8 μS − ...
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... AC,min + 2 AC,min + AC,max 1 3 − − CK(avg) IS CK(avg) − Publication Release Date: Aug. 03, 2010 - 46 - W9751G6JB 25 UNITS NOTES MAX. − t CK(avg) 0 CK(avg) 1.1 t 14,36 CK(avg) 0.6 t 14,37 CK(avg) 16,27,29, − pS 41,42,44 17,27,29, − pS 41,42,44 16,27,29, − pS 41,42,44 17,27,29, − pS 41,42,44 − t CK(avg) ...
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... Logic levels V levels REF t IS(ref) – Figure 17 Differential input waveform timing – tIS and tIH VTT = VDDQ/2 25Ω IH(base) IS(base) IH(base IH(ref) IS(ref) IH(ref W9751G6JB V DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Publication Release Date: Aug. 03, 2010 Revision A04 ...
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... DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from table of DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe (page 60). VTT + 2x mV VTT + x mV tLZ tRPRE begin point VTT - x mV VTT - tLZ,tRPRE begin point = Publication Release Date: Aug. 03, 2010 - 48 - W9751G6JB Revision A04 ...
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... WR [nCK] + tnRP [nCK {tRP [pS] / tCK(avg) [pS] }, where WR is the value programmed in the mode register set and RU stands for round up. Example: For DDR2-1066 7-7-7 at tCK(avg) = 1.875 nS with WR programmed to 8 nCK, tDAL = 8 + RU{13.125 nS / 1.875 nS} [nCK [nCK [nCK DH(base) DH(base) DS(base DH(ref) DS(ref) DH(ref W9751G6JB V DDQ V min IH(ac) V min IH(dc) V REF(dc) V max IL(dc) V max IL(ac Publication Release Date: Aug ...
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... That is, these parameters should be met whether clock jitter is present or not. 29. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U)DQS/ DQS ) crossing. W9751G6JB Publication Release Date: Aug. 03, 2010 - 50 - ...
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... N = 200 ⎡ ⎤ N ∑ tCL / (N × tCK(avg)) ⎢ ⎥ j ⎣ ⎦ where N = 200 Publication Release Date: Aug. 03, 2010 - 51 - W9751G6JB DDR2-800 DDR2-1066 UNIT MIN. MAX. MIN. MAX. -100 100 - - -200 200 -180 180 pS -160 160 -160 160 ...
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... R(2per) ⎢ for tER R(3per) ⎢ ⎢ for tER R(4per) ⎢ for tER R(5per) ⎢ ⎢ ≤ ≤ for tER R(6 – 10per) ⎢ ≤ ≤ ⎢ for tER R(11 – ⎣ Publication Release Date: Aug. 03, 2010 - 52 - W9751G6JB 50per) Revision A04 ...
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... Publication Release Date: Aug. 03, 2010 - 53 - W9751G6JB MAX UNIT pS pS tJIT(duty),max pS tJIT(duty),max Revision A04 ...
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... Timings are specified with DQs and DM input slew rate of 1.0V/nS. 42. Timings are specified with CLK/ CLK differential slew rate of 2.0 V/nS. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/nS in differential strobe mode. W9751G6JB Publication Release Date: Aug. 03, 2010 - 54 - ...
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... W9751G6JB 1.0 V/nS Unit ΔtIS ΔtIH +210 +154 pS +203 +149 pS +193 +143 pS +180 +135 pS +160 +105 pS +127 +81 pS +60 +60 pS +55 ...
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... IL(dc) V max IL(ac Δ REF(dc) Setup Slew Rate = Falling Signal TF Δ Figure 20 – Illustration of nominal slew rate for nominal slew rate TR Δ Setup Slew Rate IL(ac)max = Rising Signal Publication Release Date: Aug. 03, 2010 - 56 - W9751G6JB REF region IH(ac)min REF(dc) TR Δ IS Revision A04 ...
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... Setup Slew Rate Falling Signal = Figure 21 – Illustration of tangent line for nominal line tangent tangent line TR Δ tangent line[V Setup Slew Rate Rising Signal = - V ] REF(dc) IL(ac)max TF Δ Publication Release Date: Aug. 03, 2010 - 57 - W9751G6JB t IH line REF region - V ] IH(ac)min REF(dc) TR Δ IS Revision A04 ...
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... IL(ac Hold Slew Rate REF(dc) Rising Signal = TR Δ Figure 22 – Illustration of nominal slew rate for nominal slew rate Δ Hold Slew Rate IL(dc)max Falling Signal = Publication Release Date: Aug. 03, 2010 - 58 - W9751G6JB t IH REF region TF Δ IH(dc)min REF(dc) TF Δ IH Revision A04 ...
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... Rising Signal Figure 23 – Illustration of tangent line for tangent tangent line nominal line TR Δ REF(dc) IL(ac)max TR Δ tangent line[V Hold Slew Rate Falling Signal = Publication Release Date: Aug. 03, 2010 - 59 - W9751G6JB t IH nominal line line REF region TF Δ IH(dc)min REF(dc) TF Δ IH Revision A04 ...
Page 60
... These values are typically not subject to production test. They are verified by design and characterization. the entire table) DQS/ DQS Differential Slew Rate 1.8 V/nS 1.6 V/nS 1 - -10 - - Publication Release Date: Aug. 03, 2010 - 60 - W9751G6JB 1.2 V/nS 1.0 V/nS 0 -47 14 -35 26 -23 38 -89 -12 - -52 -140 -40 -128 -28 -116 Revision A04 - - ...
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... REF(dc) IL(ac)max = Falling Signal TF Δ Figure 24 – Illustration of nominal slew rate for tDS (differential DQS, DQS ) nominal slew rate nominal slew rate TR Δ Setup Slew Rate Rising Signal Publication Release Date: Aug. 03, 2010 - 61 - W9751G6JB REF region IH(ac)min REF(dc Δ Revision A04 ...
Page 62
... Falling Signal = Figure 25 – Illustration of tangent line for tDS (differential DQS, DQS ) nominal line tangent line tangent line TR Δ Setup Slew Rate tangent line[V = Rising Signal - V ] REF(dc) IL(ac)max TF Δ Publication Release Date: Aug. 03, 2010 - 62 - W9751G6JB REF region - V ] IH(ac)min REF(dc) TR Δ Revision A04 ...
Page 63
... Rising Signal = TR Δ Figure 26 – Illustration of nominal slew rate for tDH (differential DQS, DQS ) nominal slew rate nominal slew rate TR Δ Hold Slew Rate IL(dc)max Falling Signal = Publication Release Date: Aug. 03, 2010 - 63 - W9751G6JB REF region TF Δ IH(dc)min REF(dc) TF Δ Revision A04 ...
Page 64
... Figure 27 – Illustration tangent line for tDH (differential DQS, DQS ) tangent tangent line nominal line TR Δ REF(dc) IL(ac)max tangent line [V Hold Slew Rate = Falling Signal Publication Release Date: Aug. 03, 2010 - 64 - W9751G6JB t DH nominal line line REF region TF Δ IH(dc)min REF(dc) TF Δ Revision A04 ...
Page 65
... V DDQ V min IH(ac) V min IH(dc) V REF max IL(dc max IL(ac △TR V min - V IH(ac) REF Rising Slew = △ W9751G6JB VALUE UNIT NOTES 0 DDQ 1.0 V 1.0 V/nS MAX. UNIT NOTES VDDQ + 0.6 V 0.5 x VDDQ + 0.175 V 0.5 x VDDQ + 0.125 V V DDQ Crossing point SSQ Publication Release Date: Aug ...
Page 66
... SS −18 0.5 0.5 0.19 0.19 SSQ Maximum Amplitude DDQ /V SS SSQ Maximum Amplitude Time (nS W9751G6JB −25/25I −3 UNIT 0.5 0.5 0.5 0.5 0.66 0.8 0.66 0.8 −25/25I −3 UNIT 0.5 0.5 0.5 0.5 0.23 0.23 0.23 0.23 ...
Page 67
... TIMING WAVEFORMS 10.1 Command Input Timing CLK CLK CS RAS CAS WE A0~A12 BA0,1 10.2 Timing of the CLK Signals CLK CLK CLK CLK Refer to the Command Truth Table Publication Release Date: Aug. 03, 2010 - 67 - W9751G6JB IH(AC) V IL(AC Revision A04 ...
Page 68
... IH(ac) ODT t AOND Internal Term Res. 10.4 ODT Timing for Power Down Mode T0 T1 CLK CLK CKE IH(ac) ODT Internal Term Res. t AONPD(min) t AONPD(max IL(ac) t AOFD AON(min) t AOF(min) t AON(max IL(ac) t AOFPD(max) t AOFPD(min W9751G6JB AOF(max Publication Release Date: Aug. 03, 2010 Revision A04 ...
Page 69
... AOFD IL(ac AOFPD(max AOND IH(ac) t AONPD(max) Publication Release Date: Aug. 03, 2010 - 69 - W9751G6JB Active & Standby mode timings to be applied Power Down mode timings to be applied TT Active & Standby mode timings to be applied R TT Power Down mode timings to be applied R TT Revision A04 ...
Page 70
... T7 t AXPD t IS ODT V IL(ac) Internal Term Res ODT V IL(ac) Internal R TT Term Res IH(ac) ODT Internal Term Res IH(ac) ODT Internal Term Res. t AONPD(max) Publication Release Date: Aug. 03, 2010 - 70 - W9751G6JB T8 T9 T10 AOFD t AOFPD(max) R RTT TT t AOND R TT Revision A04 ...
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... T1 T2 CLK/CLK Posted CAS CMD NOP NOP READ A DQS, DQS DQ DQSmax NOP NOP NOP NOP NOP NOP NOP NOP W9751G6JB t RPST DQSmax NOP NOP NOP NOP NOP NOP ≤ t DQSCK Dout Dout Dout Dout Publication Release Date: Aug. 03, 2010 Revision A04 ...
Page 72
... IH DMin DMin DMin V (ac NOP NOP NOP t t DQSS DQSS t DSS DIN DIN DQSS DQSS t DSH DIN DIN DIN W9751G6JB t WPST (dc) IH DMin V (dc NOP NOP NOP Precharge Completion of The Burst Write t DSS ≥ DIN DIN DSH ≥ DIN A3 Publication Release Date: Aug. 03, 2010 ...
Page 73
... The seamless burst write operation is supported by enabling a write command every other clock for operation, every four clocks for operation. This operation is allowed regardless of same or different banks as long as the banks are activated NOP NOP NOP DOUT NOP NOP NOP DIN DIN DIN W9751G6JB NOP NOP NOP DOUT DOUT DOUT DOUT DOUT DOUT NOP NOP NOP ...
Page 74
... T4 T5 NOP NOP NOP READ B Dout Dout Dout Dout Dout NOP Write B NOP NOP Din Din Din Din Din W9751G6JB NOP NOP NOP Dout Dout Dout Dout Dout Dout Dout NOP NOP NOP Din Din Din Din Din Din Din B1 B2 ...
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... Write operation with Data Mask: WL=3, AL=0, BL=4) Data Mask Timing DQS/ DQS DQ DM CLK CLK Write CMDMAND Case 1: min t DQSS DQS/DQS DQ DM Case 2: max t DQSS DQS/DQS IH(ac) IH(ac IH(dc) IH(dc IL(dc) IL(dc IL(ac) IL(ac DQSS (min DQSS (max W9751G6JB t WR Publication Release Date: Aug. 03, 2010 Revision A04 ...
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... DQS, DQS DQ's first 4-bit prefetch second 4-bit prefetch NOP Precharge NOP Dout Dout NOP NOP NOP AL + BL/2 clks Dout Dout A0 A1 ≥ t RTP - 76 - W9751G6JB Bank A NOP NOP Activate ≥ Dout Dout Precharge NOP NOP Dout Dout Dout Dout Dout Dout Publication Release Date: Aug ...
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... NOP READA AL + BL/2 clks DQS, DQS DQ Precharge NOP NOP ≥ t RAS ≥ t RTP NOP NOP Precharge ≥ t RAS ≥ t RTP - 77 - W9751G6JB Bank A NOP NOP NOP Activate ≥ Dout Dout Dout Dout Bank A NOP NOP NOP Activate ≥ Dout Dout Dout Dout ...
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... Burst write operation followed by precharge (RL- CLK/CLK Post CAS CMD NOP WRITE A DQS, DQS DQ NOP NOP NOP DIN DIN DIN DIN W9751G6JB NOP NOP NOP Precharge Completion of the Burst Write ≥ Publication Release Date: Aug. 03, 2010 Revision A04 RTP ...
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... T5 NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN NOP NOP NOP NOP Dout Dout A0 A1 ≥ t RTP t RTP Precharge begins here - 79 - W9751G6JB NOP NOP Precharge A Completion of the Burst Write ≥ RTP Bank A NOP NOP Activate ≥ Dout Dout Dout Dout Dout ...
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... NOP NOP NOP + t RTP Dout Dout RTP Precharge begins here =3, BL=4, t RCD NOP NOP NOP Auto-precharge begins (AL + BL/ min W9751G6JB RTP Bank A NOP NOP Activate Dout Dout ≤ 2clks) RTP Bank A NOP NOP NOP Activate ≥ Dout Dout Dout Dout A0 A1 ...
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... NOP NOP NOP Auto-precharge begins ≥ Limit): WL=2, WR=2, BL= NOP NOP NOP Completion of the Burst Write DIN DIN DIN DIN W9751G6JB 2clks) RTP ≤ Bank A NOP NOP Activate t RP min. Dout Dout Dout Dout Bank A NOP NOP NOP Activate Auto-precharge Begins ≥ ...
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... Self Refresh Timing CLK CLK CKE ODT V IL(ac CMD Limit): WL=4, WR=2, BL= IL(ac AOFD Self IH(ac) IH(dc) Refresh V V IL(dc) IL(ac W9751G6JB RP Tm ≥ t XSNR ≥ t XSRD V IH(ac tIS NOP Non-Read NOP Command Command Publication Release Date: Aug. 03, 2010 Revision A04 = Read ...
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... CLK Precharge NOP CMD CKE Precharge Power Down Entry T2 Tn NOP Active Power Down Exit NOP NOP Precharge Power Down - 83 - W9751G6JB Tn+1 Tn+2 Valid NOP NOP Command t or XARD XARDS Tn+1 Tn+2 Valid NOP NOP NOP Command Exit Publication Release Date: Aug. 03, 2010 ...
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... X+1 Y Y+2 Y+1 NOP t Frequency change IS Occurs here Stable new clock before power down exit Publication Release Date: Aug. 03, 2010 - 84 - W9751G6JB Y+3 Y+4 z DLL NOP NOP Valid RESET 200 Clocks ODT is off during DLL RESET Revision A04 ...
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... BSC. 6.40 BSC. 0.80 BSC. 0.80 BSC. Note: 1. Ball land : 0.5mm --- 0.15 --- 0.20 0.10 --- - 85 - W9751G6JB aaa E B Ball Land Ball Opening 2. Ball opening : 0.4mm 3. PCB Ball land suggested 0.4mm Publication Release Date: Aug. 03, 2010 Revision A04 C 4X ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. PAGE All Initial formal data sheet Added DDR2-800, Industrial parts: W9751G6JB25I and 40~42, 45, Automotive parts: W9751G6JB25A 46, 65 40, 41 Update DC characteristics I 40~42, 45, ...