NAND04GW3B2DN6E NUMONYX, NAND04GW3B2DN6E Datasheet
NAND04GW3B2DN6E
Specifications of NAND04GW3B2DN6E
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NAND04GW3B2DN6E Summary of contents
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... ECC) – 10 years data retention RoHS compliant packages Table 1. Device summary Reference NAND04G-B2D NAND08G-BxC 1. x16 organization only available for MCP products. Rev 9 NAND04G-B2D NAND08G-BxC TSOP48 (N) LGA Part number NAND04GR3B2D NAND04GW3B2D (1) NAND04GR4B2D (1) NAND04GW4B2D NAND08GR3B2C, NAND08GW3B2C (1) NAND08GR4B2C (1) NAND08GW4B2C NAND08GR3B4C NAND08GW3B4C www.numonyx.com 1/72 1 ...
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... Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 Inputs/outputs (I/O0-I/O7 3.2 Inputs/outputs (I/O8-I/O15 3.3 Address latch enable (AL 3.4 Command latch enable (CL 3.5 Chip enable ( 3.6 Read enable ( 3.7 Write enable ( 3.8 Write protect (WP 3.9 Ready/Busy (RB 3.10 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Concurrent operations and extended read status . . . . . . . . . . . . . . . . 45 8 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 49 Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Random data input in page ...
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Contents 11 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NAND04G-B2D, NAND08G-BxC List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... TSOP48 connections for NAND04G-B2D and NAND08G-BxC . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. ULGA52 connections for NAND04G-B2D and NAND08G-B2C devices . . . . . . . . . . . . . . 12 Figure 5. ULGA52 connections for the NAND08G-B4C devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 8. Random data output during sequential data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 9. Cache read (sequential) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 10 ...
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... The NAND08G-BxC is a stacked device that combines two NAND04G-B2D dice, both of which feature a multiplane architecture. In the NAND08G-B2C devices, only one of the memory components can be enabled at a time, therefore, operations can only be performed on one of the memory components at any one time. The devices operate from a 1 voltage supply. Depending on whether the device has x16 bus width, the page size is 2112 bytes (2048 + 64 spare) or 1056 words (1024 + 32 spare), respectively ...
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... These security features are subject to an NDA (non-disclosure agreement) and are, therefore, not described in the datasheet. For more details about them, contact your nearest Numonyx sales office. For information on how to order these options, refer to scheme. Devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ’ ...
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... Command Interface E Logic WP R Command Register Figure 2. Logic diagram P/E/R Controller, High Voltage Generator I/O0-I/O7 (x8/x16) E I/O8-I/O15 (x16 NAND FLASH Description NAND Flash Memory Array Page Buffer Cache Register Y Decoder I/O Buffers & Latches I/O0-I/O7 (x8/x16) I/O8-I/O15 (x16) AI13167b AI13166b 9/72 ...
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Description Table 3. Signals names Signal I/O0-7 Data input/outputs, address inputs, or command inputs (x8/x16 devices) I/O8-15 Data input/outputs (x16 devices) AL Address Latch Enable CL Command Latch Enable E Chip Enable R Read Enable RB Ready/Busy (open-drain output) W ...
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NAND04G-B2D, NAND08G-BxC Figure 3. TSOP48 connections for NAND04G-B2D and NAND08G-BxC NAND FLASH ...
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Description Figure 4. ULGA52 connections for NAND04G-B2D and NAND08G-B2C devices 12/ ...
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NAND04G-B2D, NAND08G-BxC Figure 5. ULGA52 connections for the NAND08G-B4C devices ...
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... Memory array organization The memory array of the devices is made up of NAND structures where 32 cells are connected in series organized into blocks where each block contains 64 pages. The array is split into two areas, the main area, and the spare area. The main area of the array is used to store data, and the spare area typically stores error correction codes, software flags, or bad block identification ...
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... Second plane First plane Main area 1024 words 32 words words Page buffer, 1056 bytes 32 1024 words words words 2-page buffer 1056 bytes Memory array organization 8 bits bits 16 bits bits AI13170C 15/72 ...
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... When CL is High, the inputs are latched on the rising edge of Write Enable. 3.5 Chip enable (E) The Chip Enable input, E, activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is Low, V High while the device is busy, the device remains selected and does not go into IH standby mode ...
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... V supply voltage DD V provides the power supply to the internal core of the memory device the main DD power supply for all operations (read, program and erase). An internal voltage detector disables all functions whenever V Table 29) to protect the device from any involuntary program/erase during power-transitions. ...
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... Bus operations 4 Bus operations There are six standard bus operations that control the memory, as described in this section. SeeTable 5: Bus operations Typically, glitches of less than Chip Enable, Write Enable, and Read Enable are ignored by the memory and do not affect bus operations. 4.1 Command input Command input bus operations give commands to the memory ...
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... The Write Protect signal is not latched by Write Enable to ensure protection, even during power-up. 4.6 Standby When Chip Enable is High the memory enters standby mode, the device is deselected, outputs are disabled, and power consumption is reduced. Table 5. Bus operations ...
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Bus operations Table 7. Address insertion (x16 devices) Bus I/O7 (1) cycle A18 th 4 A26 Any additional address input cycles are ignored. 2. A29 is ...
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NAND04G-B2D, NAND08G-BxC 5 Command set All bus write operations to the device are interpreted by the command interface. The commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when the command Latch Enable signal ...
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... Device operations 6 Device operations This section provides details of the device operations. 6.1 Read memory array At power-up the device defaults to read mode. To enter read mode from another mode, the Read command must be issued (see 6.1.1 Random read Each time the Read command is issued, the first read is random read. ...
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NAND04G-B2D, NAND08G-BxC Figure 7. Read operations I/O Address Input 00h Command Code tBLBH1 30h Data Output (sequentially) Command Busy Code Device operations ai12469 23/72 ...
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Device operations Figure 8. Random data output during sequential data output tBLBH1 (Read Busy time Address 30h I/O 00h Inputs Cmd Cmd Code Code 5 Add cycles Row Add 1,2,3 Col Add 1,2 Main Area 6.2 Cache ...
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NAND04G-B2D, NAND08G-BxC After the Sequential Cache Read or Random Cache Read command has been issued, the Ready/Busy signal goes Low and the status register bits are set to SR5 =' 0' and SR6 ='0' for a period of cache read ...
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... Device operations 6.3 Page program The page program operation is the standard operation to program data to the memory array. Generally, the page is programmed sequentially, however, the device does support random input within a page recommended to address pages sequentially within a given block. The memory array is programmed by page, however, partial page programming is allowed where any number of bytes (1 to 2112) or words (1 to 1056) can be programmed ...
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NAND04G-B2D, NAND08G-BxC Figure 11. Page program operation RB I/O 80h Page Program Setup Code Figure 12. Random data input during sequential data input RB Address I/O 80h Data Intput Inputs Cmd Code 5 Add cycles Row Add 1,2,3 Col Add ...
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Device operations 6.4 Multiplane page program The devices support multiplane page program, which enables the programming of two pages in parallel, one in each plane. A multiplane page program operation requires the following two steps: 1. The first step serially ...
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... The copy back program operation is used to copy the data stored in one page and reprogram it in another page. The copy back program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. The ...
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Device operations operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. The NAND04G-B2D and NAND08G-BxC devices feature automatic EDC (error detection code) ...
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NAND04G-B2D, NAND08G-BxC Figure 15. Copy back program (with readout of data) Source I/O 00h Add Inputs Read Code tBLBH1 (Read Busy time) RB Figure 16. Page copy back program with random data input Source I/O 35h 00h Add Inputs Read ...
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Device operations Figure 17. Multiplane copy back program Read Read code code Add. 5 I/O 35h 00h 00h cycles Col. Add Row Add Source address on 1st plane Source address on 2nd plane tBLBH1 (Read ...
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NAND04G-B2D, NAND08G-BxC An erase operation consists of the following three steps (refer to 1. One bus cycle is required to set up the Block Erase command. Only addresses A18- A28 are used; all other address inputs are ignored 2. Three ...
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Device operations 6.8 Multiplane block erase The multiplane block erase operation allows the erasure of two blocks in parallel, one in each plane. This operation consists of the following three steps (refer to erase bus cycles are required ...
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NAND04G-B2D, NAND08G-BxC 6.9 Error detection code (EDC) The EDC (error detection code) is performed automatically during all program operations. It starts immediately after the device becomes busy. The EDC detects 1 single bit error per EDC unit. Each EDC unit ...
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... The Reset command is used to reset the command interface and status register. If the Reset command is issued during any operation, the operation is aborted. If the aborted operation is a program or erase, the contents of the memory locations being modified are no longer valid as the data is partially programmed or erased. ...
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... The error bit identifies if any errors have been detected by the P/E/R controller. The error bit is set to ’1’ when a program or erase operation has failed to write the correct data to the memory. If the error bit is set to ‘0’ the operation has completed successfully. 6.11.5 SR4, SR3, SR2 and SR1 are reserved Table 14 ...
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Device operations 6.12 Read status enhanced In NAND flash devices with multiplane architecture possible to independently read the status register of a single plane using the Read Status Enhanced command. If the error bit of the status register, ...
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NAND04G-B2D, NAND08G-BxC 6.14 Read electronic signature The devices contain a manufacturer code and device code. The following three steps are required to read these codes: 1. One bus write cycle to issue the Read Electronic Signature command (90h) 2. One ...
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Device operations Table 18. Electronic signature byte 4 I/O I/O1-I/O0 (without spare area) Spare area size I/O2 (byte/512 byte) Minimum sequential access I/O7, I/O3 I/O5-I/O4 (without spare area) I/O6 Table 19. Electronic signature byte 5 I/O I/O1 - I/O0 I/O3 ...
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NAND04G-B2D, NAND08G-BxC 6.15 Read ONFI signature To recognize NAND flash devices that are compatible with the ONFI 1.0 command set, the Read Electronic Signature can be issued, followed by an address of 20h. The next four bytes output is the ...
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Device operations Table 21. Parameter page data structure Byte O/M 0-3 4-5 6-7 8-9 10-31 32-43 44-63 64 65-66 67-79 80-83 84-85 86-89 90-91 92-95 42/72 (1) Parameter page signature – Byte 0: 4Fh, ‘O’ M – Byte 1: 4Eh, ...
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NAND04G-B2D, NAND08G-BxC Table 21. Parameter page data structure (continued) Byte O/M 96-99 100 101 102 103-104 105-106 107 108-109 110 111 112 113 114 115-127 128 (1) M Number of blocks per logical unit (LUN) M Number of logical units ...
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Device operations Table 21. Parameter page data structure (continued) Byte O/M 129-130 131-132 133-134 135-136 137-138 139-163 164-165 166-253 254-255 256-511 512-767 768 optional mandatory. 44/72 (1) Timing mode support Bit 6 to bit 15 ...
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NAND04G-B2D, NAND08G-BxC 7 Concurrent operations and extended read status The NAND08G-BxC devices are composed of two 4-Gbit dice stacked together. This configuration allows the devices to support concurrent operations, which means that while performing an operation in one die (erase, ...
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... Implementation of a garbage collection, a wear-leveling algorithm and an error correction code is recommended. To help integrate a NAND memory into an application, Numonyx provides a file system OS native reference software, which supports the basic commands of file management. Contact the nearest Numonyx sales office for more details. ...
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... The Copy Back Program command can be used to copy the data to a valid block. See Read failure In this case, ECC correction must be implemented. To efficiently use the memory space, the recovery of a single-bit error in read by ECC, without replacing the whole block, is recommended. ...
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... After several updates it is necessary to remove invalid pages to free memory space. To free this memory space and allow further program operations, the implementation of a garbage collection algorithm is recommended. In garbage collection software, the valid pages are copied into a free area and the block containing the invalid pages is erased as ...
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NAND04G-B2D, NAND08G-BxC 10 Program and erase times and endurance cycles The program and erase times and the number of program/erase cycles per block are shown in Table 24. Table 24. Program erase times and program erase endurance cycles Parameters Page ...
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Maximum ratings 11 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the ...
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NAND04G-B2D, NAND08G-BxC 12 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the devices. The parameters in the following DC and AC characteristics tables are derived from tests performed under ...
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DC and AC parameters Figure 23. Equivalent testing circuit for AC characteristics measurement Table 28. DC characteristics (1.8 V devices) Symbol Parameter I DD1 Operating I current DD2 I DD3 I Standby current (CMOS) DD5 I Input leakage current LI ...
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NAND04G-B2D, NAND08G-BxC Table 29. DC characteristics (3 V devices) Symbol Parameter I DD1 Operating I current DD2 I DD3 Standby current (TTL) I DD4 I Standby current (CMOS) DD5 I Input leakage current LI I Output leakage current LO V ...
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DC and AC parameters Table 31. AC characteristics for operations Symbol Alt. t Address Latch Low to Read ALLRL1 t AR Enable Low t ALLRL2 t t Ready/Busy High to Read Enable Low BHRL RR t BLBH1 t t BLBH2 ...
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NAND04G-B2D, NAND08G-BxC Figure 24. Command latch AC waveforms CL tCLHWH (CL Setup time) tELWH H(E Setup time tALLWH (ALSetup time) AL I/O Figure 25. Address latch AC waveforms CL tELWH (E Setup time) E tWLWH W tWHWL tALHWH ...
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DC and AC parameters Figure 26. Data input latch AC waveforms CL E tALLWH (ALSetup time) AL tWLWH W (Data Setup time) I/O 1. The last data input is the 2112th. Figure 27. Sequential data output after read AC waveforms ...
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NAND04G-B2D, NAND08G-BxC Figure 28. Sequential data output after read AC waveforms (EDO mode) E tRLRH R tELQV tRLQV (R Accesstime) I/O tBHRL EDO mode, CL and AL are Low applicable for frequencies high ...
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DC and AC parameters Figure 30. Read status enhanced waveform I/O 0-7 78h Address 1 Figure 31. Read electronic signature AC waveform I/O 90h Read Electronic Signature Command 1. Refer to ...
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NAND04G-B2D, NAND08G-BxC Figure 32. Read ONFI signature waveform I/O 90h Read Electronic Signature command tALLRL1 tRLQV (Read ES access time) 4Fh 20h 4Eh 1st cycle address DC and AC parameters 46h 49h XXh ai13178b 59/72 ...
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DC and AC parameters Figure 33. Page read operation AC waveform CL E tWLWL Add.N Add.N Add.N I/O 00h cycle 1 cycle 2 cycle 3 Command Address N Input Code 60/72 tWHBL tALLRL2 tWHBH tRLRH tBLBH1 ...
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NAND04G-B2D, NAND08G-BxC Figure 34. Page program AC waveform CL E tWLWL (Write Cycle time Add.N Add.N I/O 80h cycle 1 cycle 2 RB Page Program Setup Code tWLWL tWHWH Add.N Add.N Add.N N cycle 4 cycle 5 ...
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DC and AC parameters Figure 35. Block erase AC waveform CL E tWLWL (Write Cycle time Add. I/O 60h cycle 1 RB Block Erase Block Address Input Setup Command Figure 36. Reset AC waveform ...
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NAND04G-B2D, NAND08G-BxC Figure 37. Program/erase enable waveform W tVHWH WP RB I/O 80h Program setup Figure 38. Program/erase disable waveform W tVLWH WP High RB I/O Program disable I High RB I/O 80h DC and ...
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DC and AC parameters Figure 39. Read parameter page waveform I/O0-7 ECh R/B 64/72 00h tBLBH1 NAND04G-B2D, NAND08G-BxC ... ... ai14409 ...
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NAND04G-B2D, NAND08G-BxC 12.1 Ready/busy signal electrical characteristics Figure 41, Figure 40 signal. The value required for the resistor R This is an example for 3 V devices: where I is the sum of the input currents of all the devices ...
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... DC and AC parameters Figure 42. Resistor value versus waveform timings for ready/busy signal °C. 12.2 Data protection The Numonyx NAND devices are designed to guarantee data protection during power transitions detection circuit disables all NAND operations the V range from V DD low ( guarantee hardware protection during power transitions as shown in the below IL figure ...
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... NAND04G-B2D, NAND08G-BxC 13 Package mechanical To meet environmental requirements, Numonyx offers these devices in RoHS compliant packages, which have a lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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Package mechanical Figure 45. ULGA52 0.65 mm pitch, package outline FE1 Drawing is not to scale. Table 33. ULGA52 0.65 mm pitch, ...
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... F = RoHS compliant package, tape and reel packing 1. x16 organization only available for MCP products Note: Not all combinations are necessarily available. For a list of available devices of for further information on any aspect of these products, please contact your nearest Numonyx sales office. Ordering information NAND04GW3B2D N ...
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... Table 1, Table 2, Table – Added Figure 5: ULGA52 connections for the NAND08G-B4C devices. Changed VLKO value in 3 Applied Numonyx branding. Modified: Figure 6: Memory array Multiplane page program back program, Figure 19: Multiplane block Read status enhanced enable waveform, Figure 38: Program/erase disable and ...
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... Section 9.5: Error correction 8 back program. Removed Fig.23 Error detection. Removed Note 1 below Logic diagram, Table 3: Signals 9 connections for the NAND08G-B4C Modified Figure 6: Memory array Revision history Changes Section 1: Description, Section 9.1: Note 1 below Table 28 and Table code, Figure 17: Multiplane copy ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...