CY7C1061DV33-10ZSXI Cypress Semiconductor Corp, CY7C1061DV33-10ZSXI Datasheet

IC SRAM 16MBIT 10NS 54TSOP

CY7C1061DV33-10ZSXI

Manufacturer Part Number
CY7C1061DV33-10ZSXI
Description
IC SRAM 16MBIT 10NS 54TSOP
Manufacturer
Cypress Semiconductor Corp
Type
Asynchronousr
Datasheet

Specifications of CY7C1061DV33-10ZSXI

Memory Size
16M (1M x 16)
Package / Case
54-TSOP II
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Speed
10ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Access Time
10 ns
Supply Voltage (max)
4.6 V
Supply Voltage (min)
2 V
Maximum Operating Current
175 mA
Organization
1 M x 16
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
3.3 V
Density
16Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
20b
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Supply Current
175mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
54
Word Size
16b
Number Of Words
1M
Rohs Compliant
YES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2960-5
CY7C1061DV33-10ZSXI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1061DV33-10ZSXI
Manufacturer:
CYPRES21
Quantity:
76
Part Number:
CY7C1061DV33-10ZSXI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Features
Selection Guide
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 38-05476 Rev. *G
Maximum access time
Maximum operating current
Maximum CMOS standby current
High speed
Low active power
Low CMOS standby power
Operating voltages of 3.3 ± 0.3V
2.0V data retention
Automatic power down when deselected
TTL compatible inputs and outputs
Easy memory expansion with CE
Available in Pb-free 54-pin TSOP II and 48-ball VFBGA
packages
Offered in single CE and dual CE options
t
I
I
AA
CC
SB2
= 10 ns
= 175 mA at 10 ns
= 25 mA
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
1
Description
and CE
INPUT BUFFER
DECODER
COLUMN
2
1M x 16
ARRAY
features
198 Champion Court
Functional Description
The CY7C1061DV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
A
(I/O
address pins (A
To read from the device, take Chip Enables (CE
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O
memory appears on I/O
12
The input or output pins (I/O
impedance state when the device is deselected (CE
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, CE
The CY7C1061DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and 48-ball
VFBGA packages.
19
16-Mbit (1 M x 16) Static RAM
for a complete description of Read and Write modes.
). If Byte High Enable (BHE) is LOW, then data from I/O pins
8
through I/O
0
to I/O
2
HIGH, and WE LOW).
San Jose
7
. If Byte High Enable (BHE) is LOW, then data from
I/O
I/O
0
15
0
8
through A
– I/O
– I/O
BHE
WE
OE
BLE
) is written into the location specified on the
,
7
15
CA 95134-1709
8
to I/O
–10
175
19
10
25
0
).
through I/O
15
. See the
CE
CE
CY7C1061DV33
2
1
Revised January 18, 2011
15
0
) are placed in a high
Truth Table on page
through I/O
1
LOW and CE
1
LOW and CE
408-943-2600
Unit
mA
mA
ns
1
HIGH/CE
0
7
through
), is
2
2
2
1
[+] Feedback

Related parts for CY7C1061DV33-10ZSXI

CY7C1061DV33-10ZSXI Summary of contents

Page 1

... LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, CE HIGH, and WE LOW). 2 The CY7C1061DV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and 48-ball VFBGA packages. INPUT BUFFER I/O ...

Page 2

... Capacitance ...................................................................... 7 AC Switching Characteristics ......................................... 8 Data Retention Characteristics ....................................... 9 Over the Operating Range ............................................... 9 Switching Waveforms ...................................................... 9 Truth Table ...................................................................... 12 Document Number: 38-05476 Rev. *G CY7C1061DV33 Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagrams .......................................................... 14 Acronyms ........................................................................ 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products ...

Page 3

... In BVXI package, ball H6 is MSB address A19 and ball G2 is NC; in BVJXI package, ball and ball G2 is MSB address A19. Document Number: 38-05476 Rev BLE I/O BHE I I/O A I/O I I I/O I/O A I/O I I BLE I/O BHE CE I I/O I/O I I I/O I/O I CY7C1061DV33 [1, 2] [1, 2] Page [+] Feedback ...

Page 4

... Note 3. NC pins are not connected on the die. Document Number: 38-05476 Rev. *G [3] Figure 3. 54-Pin TSOP II (Top View) I/O I I/O I I BHE BLE I I/O I I I CY7C1061DV33 Page [+] Feedback ...

Page 5

... In BV1XI package, ball A6 is NC, ball and ball G2 is MSB address A19. BV1XI package has only single Chip Enable (CE). Document Number: 38-05476 Rev BLE I/O 8 BHE I/O 9 I/O 1 I I I CY7C1061DV33 [4, 5] Page [+] Feedback ...

Page 6

... IL, V > < MAX Max > V – 0.3V, CE < 0.3V > V – 0.3V < 0.3V CY7C1061DV33 Ambient V CC Temperature –40 C to +85 C 3.3 V  0.3 V –10 Unit Min Max 2.4 – V – 0 –0.3 0.8 V A –1 +1 A –1 +1 175 mA – ...

Page 7

... Test Conditions = 25  MHz 3 Test Conditions Figure 5. AC Test Loads and Waveforms High-Z Characteristics All Input Pulses 90% 90% 10% (c) > 1 V/ns to the data retention (V , 2.0 V) voltage. DD CCDR CY7C1061DV33 TSOP II VFBGA Unit TSOP II VFBGA Unit C/W 24.18 28.37 C/W 5.40 5.79 [7] R1 317  ...

Page 8

... Waveforms[7], unless specified otherwise. values until the first memory access is performed. CC are specified with a load capacitance (b) of LZBE = V , and Chip enables must be active and WE and byte enables must be LOW and t HZWE CY7C1061DV33 –10 Unit Min Max s 100 – 10 – ns – – ...

Page 9

... CDR [17, 18] Figure 7. Read Cycle No OHA > 50 s or stable at V > 50  CC(min.) CC(min.) and CE . When CE is LOW and BHE, BLE or both = CY7C1061DV33 Min Max 2 – – 25 < 0 – t – RC [16] 3 Data Valid is HIGH LOW; when CE is HIGH Page Unit V mA ...

Page 10

... If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 38-05476 Rev ACE t DOE t LZOE t DBE t LZBE Data Valid 50 SCE PWE and CE . When CE is LOW and CY7C1061DV33 [19, 20, 21] t HZOE t HZCE t HZBE High Impedance t PD 50% [19, 22, 23 HIGH LOW; when CE is HIGH LOW Page ICC CC I ISB SB [+] Feedback ...

Page 11

... Data I/O is high impedance if OE, BHE, and/or BLE = V 26 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 38-05476 Rev SCE PWE HZWE PWE t SCE t SD and CE . When CE is LOW and CY7C1061DV33 [24, 25, 26 LZWE [24 HIGH LOW; when CE is HIGH LOW Page [+] Feedback ...

Page 12

... High Z Read lower bits only High Z Data out Read upper bits only Data in Data in Write all bits Data in High Z Write lower bits only High Z Data in Write upper bits only High Z High Z Selected, outputs disabled CY7C1061DV33 Power Standby ( Standby ( Active ( Active ( Active ( ...

Page 13

... Ordering Information Speed Ordering Code (ns) 10 CY7C1061DV33-10ZSXI CY7C1061DV33-10BVXI CY7C1061DV33-10BVJXI CY7C1061DV33-10BV1XI Ordering Code Definitions V33 - 10 XXX Document Number: 38-05476 Rev. *G Package Package Type Diagram 51-85160 54-pin TSOP II (Pb-free) 51-85178 48-ball VFBGA (8 × 9.5 × 1 mm) (Pb-free) (Dual Chip Enable) 48-ball VFBGA (8 × 9.5 × 1 mm) (Pb-free) (Dual Chip Enable - JEDEC compatible) 48-Ball VFBGA (8 × ...

Page 14

... Package Diagrams Document Number: 38-05476 Rev. *G Figure 12. 54-Pin TSOP Type II CY7C1061DV33 51-85160 *A Page [+] Feedback ...

Page 15

... CE chip enable I/O input/output OE output enable SRAM static random access memory TSOP thin small outline package VFBGA very fine ball gird array WE write enable Document Number: 38-05476 Rev. *G Figure 13. 48-Ball VFBGA ( mm) CY7C1061DV33 51-85178 *A Page [+] Feedback ...

Page 16

... Document History Page Document Title: CY7C1061DV33 16-Mbit ( 16) Static RAM Document Number: 38-05476 Orig. of Submission Rev. ECN No. Change Date ** 201560 SWI See ECN *A 233748 RKF See ECN *B 469420 NXR See ECN *C 499604 NXR See ECN *D 1462583 VKN/AESA See ECN *E 2704415 VKN/PYRS 05/11/09 ...

Page 17

... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05476 Rev. *G All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised January 18, 2011 CY7C1061DV33 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...

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