CY7C1061AV33-10ZXC Cypress Semiconductor Corp, CY7C1061AV33-10ZXC Datasheet

IC SRAM 16MBIT 10NS 54TSOP

CY7C1061AV33-10ZXC

Manufacturer Part Number
CY7C1061AV33-10ZXC
Description
IC SRAM 16MBIT 10NS 54TSOP
Manufacturer
Cypress Semiconductor Corp
Type
Asynchronousr
Datasheet

Specifications of CY7C1061AV33-10ZXC

Memory Size
16M (1M x 16)
Package / Case
54-TSOP II
Interface
Parallel
Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Speed
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Access Time
10 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Maximum Operating Current
275 mA
Organization
1 M x 16
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Ports
1
Operating Supply Voltage
3.3 V
Density
16Mb
Access Time (max)
10ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
20b
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Supply Current
275mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
54
Word Size
16b
Number Of Words
1M
Memory Configuration
1M X 16
Supply Voltage Range
3V To 3.6V
Memory Case Style
TSOP
No. Of Pins
54
Operating Temperature Range
0°C To +70°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-1983
CY7C1061AV33-10ZXC

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C1061AV33-10ZXC
Manufacturer:
INFINEON
Quantity:
1 450
Part Number:
CY7C1061AV33-10ZXC
Manufacturer:
CYPRESS
Quantity:
1 016
16-Mbit (1 M × 16) Static RAM
Features
Cypress Semiconductor Corporation
Document #: 38-05256 Rev. *K
Logic Block Diagram
High speed
Low active power
Operating voltages of 3.3 ± 0.3 V
2.0 V data retention
Automatic power down when deselected
TTL compatible inputs and outputs
Easy memory expansion with CE
Available in Pb-free and non Pb-free 54-pin TSOP II package
and non Pb-free 60-ball fine-pitch ball grid array (FBGA)
package
t
990 mW (max)
AA
= 10 ns
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
1
and CE
INPUT BUFFER
DECODER
COLUMN
2
1M x 16
ARRAY
features
198 Champion Court
Functional Description
The CY7C1061AV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, enable the chip (CE
while forcing the Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O
is written into the location specified on the address pins (A
through A
I/O pins (I/O
on the address pins (A
To read from the device, enable the chip by taking CE
CE
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins will
appear on I/O
data from memory will appear on I/O
on page 8
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH/CE
and BLE are disabled (BHE, BLE HIGH), or a Write operation is
in progress (CE
16-Mbit (1 M × 16) Static RAM
2
HIGH while forcing the Output Enable (OE) LOW and the
2
19
for a complete description of Read and Write modes.
LOW), the outputs are disabled (OE HIGH), the BHE
San Jose
). If Byte High Enable (BHE) is LOW, then data from
8
through I/O
0
I/O
I/O
to I/O
1
0
8
LOW, CE
–I/O
–I/O
BHE
WE
OE
BLE
7
,
7
15
. If Byte High Enable (BHE) is LOW, then
0
CA 95134-1709
through A
15
2
) is written into the location specified
0
HIGH, and WE LOW).
through I/O
19
CE
CE
).
CY7C1061AV33
8
2
1
to I/O
Revised April 11, 2011
1
15
LOW and CE
15
) are placed in a
. See
0
408-943-2600
through I/O
Truth Table
1
LOW and
2
HIGH)
7
),
0
1
[+] Feedback

Related parts for CY7C1061AV33-10ZXC

CY7C1061AV33-10ZXC Summary of contents

Page 1

... Cypress Semiconductor Corporation Document #: 38-05256 Rev. *K 16-Mbit (1 M × 16) Static RAM Functional Description The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. To write to the device, enable the chip (CE while forcing the Write Enable (WE) input LOW. If Byte Low ...

Page 2

... Read Cycle No. 1 (Address Transition Controlled) ...... 6 Read Cycle No. 2 (OE Controlled) .............................. 6 Write Cycle No. 1 (CE1 or CE2 Controlled) ................ 7 Write Cycle No. 2 (WE Controlled, OE LOW) ............. 7 Write Cycle No. 3 (BHE/BLE Controlled) .................... 8 Document #: 38-05256 Rev. *K CY7C1061AV33 Truth Table ........................................................................ 8 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Diagrams .......................................................... 10 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ...

Page 3

... NC pins are not connected on the die. 2. DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper operation. Document #: 38-05256 Rev. *K –10 10 Commercial 275 Industrial 275 Commercial/Industrial I I I CY7C1061AV33 Unit 54-pin TSOP II (Top View) I/O I I/O I I/O I I/O I ...

Page 4

... V CC [ components of the test environment. ALL INPUT PULSES 90% 90% 10% 10% Fall time: > 1 V/ns (c) to the data retention (V DD CY7C1061AV33 [3] ............................. –0 0 Ambient V CC Temperature 0 C to +70 C 3.3 V  0.3 V –40 C to +85 C –10 Min Max 2.4 – – ...

Page 5

... Read/Write operation is started. power , t are specified with a load capacitance (b) of LZBE LOW (CE HIGH) and WE LOW. Chip enables must be active and WE and byte enables must 1 2 and t HZWE CY7C1061AV33 –10 Unit Min Max 1 – – ns – 10 ...

Page 6

... WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE transition LOW and CE 1 Document #: 38-05256 Rev. *K DATA RETENTION MODE 3 > [12, 13 OHA DBE t DOE DATA VALID 50% . CE2 = transition HIGH. 2 CY7C1061AV33 3 DATA VALID HZCE t HZBE t HZOE HIGH IMPEDANCE Page [+] Feedback ...

Page 7

... HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 1 17. During this period, the IOs are in output state and input signals should not be applied. Document #: 38-05256 Rev. *K [15, 16 SCE PWE VALID DATA [15, 16 SCE PWE t SD VALID DATA . IH CY7C1061AV33 LZWE Page [+] Feedback ...

Page 8

... High Z Read Lower Bits Only High Z Data Out Read Upper Bits Only Data In Data In Write All Bits Data In High Z Write Lower Bits Only High Z Data In Write Upper Bits Only High Z High Z Selected, Outputs Disabled CY7C1061AV33 Mode Power Standby ( Standby ( Active ( Active (I ...

Page 9

... The following table lists the CY7C1061AV33 key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Speed (ns) Ordering Code 10 CY7C1061AV33-10ZXC CY7C1061AV33-10ZXI CY7C1061AV33-10BAXI Ordering Code Definitions ...

Page 10

... Package Diagrams Figure 1. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm), 51-85160 Document #: 38-05256 Rev. *K CY7C1061AV33 51-85160 *A Page [+] Feedback ...

Page 11

... Package Diagrams (continued) Figure 2. 60-ball FBGA (8 × 20 × 1.2 mm), 51-85162 Document #: 38-05256 Rev. *K CY7C1061AV33 51-85162 *E Page [+] Feedback ...

Page 12

... I/O input/output OE output enable SRAM static random access memory TSOP thin small-outline package TTL transistor-transistor logic WE Write Enable Document #: 38-05256 Rev. *K CY7C1061AV33 Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V Volts µA micro Amperes mA milli Amperes mm ...

Page 13

... Document History Page Document Title: CY7C1061AV33 16-Mbit (1 M × 16) Static RAM Document Number: 38-05256 Submission Revision ECN Date ** 113725 03/28/02 *A 117058 07/31/02 *B 117989 08/30/02 *C 120383 11/06/02 *D 124439 2/25/03 *E 492137 See ECN *F 508117 See ECN *G 877322 See ECN *H 2897049 03/22/10 *I 3109147 12/13/2010 ...

Page 14

... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05256 Rev. *K All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised April 11, 2011 CY7C1061AV33 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...

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