CY7C057V-12AC Cypress Semiconductor Corp, CY7C057V-12AC Datasheet
CY7C057V-12AC
Specifications of CY7C057V-12AC
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CY7C057V-12AC Summary of contents
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... Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • 16K x 36 organization (CY7C056V) • 32K x 36 organization (CY7C057V) • 0.25-micron CMOS for optimum speed/power • High-speed access: 12/15/20 ns • Low operating power — Active: I ...
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... Control of a semaphore indicates that a shared re- source is in use. An automatic Power-Down feature is con- trolled independently on each port by Chip Select ( pins. 1 The CY7C056V and CY7C057V are available in 144-Pin Thin Quad Plastic Flatpack (TQFP) and 172-Ball Ball Grid Array (BGA) packages. . CY7C056V CY7C057V ...
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... A11L A12L 31 A13L 32 [ I/O26L 34 I/O25L 35 I/O24L 36 Notes: 4. This pin is A14L for CY7C057V. 5. This pin is A14R for CY7C057V. Document #: 38-06055 Rev. ** 144-Pin Thin Quad Flatpack (TQFP) Top View CY7C056V (16K x 36) CY7C057V (32K x 36) CY7C056V CY7C057V 108 I/O33R I/O34R 107 106 I/O35R ...
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... I/O25L I/O19L VSS VSS I/O22L I/O18L NC I/O7L I/O2L I/O2R I/O8L I/O6L I/O5L I/O3L I/O0L I/O0R NC VSS I/O4L VDD I/O1L I/O1R CY7C056V CY7C057V VDD I/O13R VSS NC I/O30R I/O32R I/O12R I/O14R I/O17R I/O29R I/O33R A0R NC I/O27R I/O31R A1R NC I/O16R I/O28R I/O34R I/O35R A3R A2R ...
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... Power Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Industrial +0.5V DD [6] Shaded areas contain advance information. +0.5V DD CY7C056V CY7C057V CY7C056V CY7C056V CY7C057V CY7C057V -15 - 240 230 Description –A for 32K devices and CE V ...
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... Industrial Commercial [9] MAX Industrial Test Conditions MHz 3. LOW. 1 (except Output Enable means no address or control lines change. This applies only to inputs at CMOS level CY7C056V CY7C057V CY7C056V CY7C057V -12 -15 -20 2.4 2.4 0.4 0.4 2.0 2.0 0.8 0.8 10 –10 10 –10 250 385 240 360 ...
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... Normal Load (Load 1) ALL INPUT PULSES Notes: 11. External AC Test Load Capacitance = 10 pF. 12. (Internal I/O pad Capacitance = 10 pF Test Load. Document #: 38-06055 Rev 1.5V TH (b) Three-State Delay (Load 2) 3.0V 90% 10 [12 100 200 Capacitance (pF) (b) Load Derating Curve CY7C056V CY7C057V 3. 590 OUTPUT 435 90% 10 Page ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. Document #: 38-06055 Rev. ** [13] CY7C056V CY7C057V -12 -15 Min. Max. Min. Max less than t and t is less than t HZCE LZCE HZOE LZOE CY7C056V CY7C057V -20 Min. Max. Unit time. SCE . Page ...
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... Busy Timing t BUSY LOW from Address Match BLA t BUSY HIGH from Address Mismatch BHA t BUSY LOW from CE LOW BLC Note: 19. Test conditions used are Load 1. Document #: 38-06055 Rev. ** [13] (continued) CY7C056V CY7C057V -12 -15 Min. Max. Min. Max CY7C056V CY7C057V -20 Min. Max. Unit Page ...
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... SEM Flag Contention Window SPS t SEM Address Access Time SAA Data Retention Mode The CY7C056V and CY7C057V are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: [3] 1. Chip Enable (CE) ...
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... LZCE , and WA, BA are valid. This waveform cannot be used for semaphore reads transition LOW and CE transition HIGH WA, BA are valid, and SEM = access semaphore CY7C056V CY7C057V t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE t HZCE = and SEM = and SEM Page ...
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... CHIP SELECT VALID t SCE and SEM=V and B PWE 0–3 or R/W or (SEM or R/W) going HIGH at the end of Write Cycle PWE . IH =SEM = =SEM = =SEM = =SEM = CY7C056V CY7C057V [33] t HZOE LZWE NOTE LOW allow the I/O drivers to turn off and data to be placed on HZWE SD . PWE Page ...
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... SPS Document #: 38-06055 Rev. ** [36 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [37, 38, 39] MATCH t SPS MATCH = CE = HIGH and =LOW CY7C056V CY7C057V t t SAA OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE Page ...
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... Timing Diagram of Write with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 40 LOW HIGH Document #: 38-06055 Rev. ** [40 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C056V CY7C057V BHA t BDD t DDD VALID t WDD Page ...
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... BUSY will be asserted. PS Document #: 38-06055 Rev. ** [41] ADDRESS MATCH CHIP SELECT VALID t PS CHIP SELECT VALID t BLC ADDRESS MATCH CHIP SELECT VALID t PS CHIP SELECT VALID t BLC [41 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C056V CY7C057V t BHC t BHC Page ...
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... Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INT : R ADDRESS WRITE 3FFF (7FFF for CY7C057V CHIP SELECT VALID R/W L INT R [43] t INS Right Side Clears INT : R ADDRESS R INT R : Right Side Sets INT L ADDRESS WRITE 3FFE (7FFE for CY7C057V R/W R INT ...
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... Architecture The CY7C056V and CY7C057V consist of an array of 16K and 32K words of 36 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE control pins permit independent access for reads or writes to any lo- cation in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port ...
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... Left Port Writes 1 to Semaphore Right Port Writes 0 to Semaphore Right Port Writes 1 to Semaphore Left Port Writes 0 to Semaphore Left Port Writes 1 to Semaphore Notes: 44. A and A , 7FFF/7FFE for the CY7C057V. 0L–14L 0R–14R 45. If BUSY =L, then no change. R 46. If BUSY =L, then no change. L Document #: 38-06055 Rev. ** ...
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... If both ports attempt to access the semaphore within t be obtained by one side or the other, but there is no guarantee which side will control the semaphore. CY7C056V CY7C057V I/O Pins Used I/O 0–35 I/O 0–35 I/O 0– ...
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... Bus Match Operation The right port of the CY7C057V 32Kx36 dual-port SRAM can be configured in a 36-bit long-word, 18-bit word, or 9-bit byte format for data I/O. The data lines are divided into four lanes, each consisting of 9 bits (byte-size data lines). 9 CY7C056V / 9 CY7C057V ...
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... Ordering Information Speed (ns) Ordering Code 12 CY7C056V-12AC CY7C056V-12BBC 15 CY7C056V-15AC CY7C056V-15BBC 20 CY7C056V-20AC CY7C056V-20BBC Speed (ns) Ordering Code 12 CY7C057V-12AC CY7C057V-12BBC 15 CY7C057V-15AC CY7C057V-15AI CY7C057V-15BBC CY7C057V-15BBI 20 CY7C057V-20AC CY7C057V-20BBC Package Diagrams Document #: 38-06055 Rev. ** Package Name A144 144-Pin Thin Quad Flat Pack BB172 172-Ball Ball Grid Array (BGA) ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 172-Ball BGA BB172 CY7C056V CY7C057V Page ...
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... Document Title: CY7C056V/CY7C057V 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static RAM Document Number: 38-06055 Issue REV. ECN NO. Date ** 110214 12/16/01 Document #: 38-06055 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00742 to 38-06055 CY7C056V CY7C057V Page ...