CY7C09179V-12AC Cypress Semiconductor Corp, CY7C09179V-12AC Datasheet

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... Automatic power-down • Commercial and Industrial temperature ranges • Available in 100-pin TQFP 0 I/O I/O Control Control True Dual-Ported RAM Array for 128K devices. 16 • 3901 North First Street • CY7C09079V/89V/99V CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9 [1] [ 0/1 8/9 I/O 15/16/ ...

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... Functional Description The CY7C09079V/89V/99V and CY7C09179V/89V/99V are high-speed synchronous CMOS 32K, 64K, and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting in- dependent, simultaneous access for reads and writes to any [4] location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined out- put mode, data is registered for decreased cycle time ...

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... A) (Both rent for I SB3 Ports CMOS Level) Notes: 8. This pin is NC for CY7C09179V. 9. This pin is NC for CY7C09179V and CY7C09189V. Document #: 38-06043 Rev pin compatible with an IDT 5V x8 pipelined device; connecting pin #23 and #53 to GND is CC 100-Pin TQFP (Top View ...

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... V and –I/O for x8 devices; I Output Current into Outputs (LOW)20 mA Static Discharge Voltage>2001V Latch-Up Current>200 mA Operating Range Range +0.5V Commercial Industrial CY7C09079V/89V/99V CY7C09179V/89V/99V –A for 128K devices AND CE must be asserted –I/O for x9 devices Ambient Temperature +70 C 3.3V [11] – +85 C 3.3V . MAX V CC ...

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... Ind. Com’l. 10 250 [11] Ind. Com’l. 105 135 [11] Ind. Description Test Conditions MHz 3.3V CC AND CE 0 CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V [ 2.4 2.4 0.4 0.4 2.0 2.0 0.8 0.8 10 –10 10 –10 155 275 135 225 275 390 185 295 25 85 ...

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... Note: 13. Test Conditions pF. Document #: 38-06043 Rev 250 TH OUTPUT (b) Thévenin Equivalent (Load 1) [13] 3.0V GND = 1. Capacitance (pF) (b) Load Derating Curve CY7C09079V/89V/99V CY7C09179V/89V/99V OUTPUT 1.4V TH (c) Three-State Delay (Load 2) (Used for CKLZ including scope and jig) ALL INPUT PULSES 90% 90% 10% 10 ...

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... CKLZ Port to Port Delays t Write Port Clock HIGH to Read Data Delay CWDD t Clock to Clock Set-Up Time CCS Notes: 14. Test conditions used are Load 2. 15. This parameter is guaranteed by design, but it is not production tested. Document #: 38-06043 Rev. *A CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09079V/89V/99V CY7C09179V/89V/99V [1] [ 100 ...

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... Q n [16, 17, 18, 19 CYC2 t CL2 A A n+1 t CD2 Q t CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09079V/89V/99V CY7C09179V/89V/99V n+2 n+3 t CKHZ Q Q n+1 n OHZ OLZ n+2 ...

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... CWDD Document #: 38-06043 Rev. *A CL2 CD2 HC CD2 [22, 23, 24, 25 MATCH CD1 CWDD . for the left port, which is being written to. IH CY7C09079V/89V/99V CY7C09179V/89V/99V CD2 CKHZ CKLZ CD2 CKHZ CKLZ NO NO MATCH t CD1 VALID >maximum specified, then data is not CWDD CCS CKHZ CD2 D ...

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... During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity. Document #: 38-06043 Rev. *A [19, 26, 27, 28 n+1 n CD2 CKHZ Q n READ NO OPERATION [19, 26, 27, 28 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE . IH CY7C09079V/89V/99V CY7C09179V/89V/99V A A n+3 n CKLZ WRITE READ A A n+4 n CKLZ CD2 READ Page CD2 Q n+3 Q n+4 ...

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... Document #: 38-06043 Rev. *A [17, 19, 26, 27, 28 n+1 n CD1 CKHZ NO READ OPERATION [17, 20, 26, 27, 28 n OHZ READ CY7C09079V/89V/99V CY7C09179V/89V/99V n+2 n n+2 t CD1 Q n CKLZ DC WRITE READ A A n+3 n CD1 CKLZ DC WRITE READ A n+4 t CD1 A n+5 t CD1 n+4 Page ...

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... R/W and CNTRST = Document #: 38-06043 Rev. *A [29] t SAD t SCN t CD2 READ WITH COUNTER [29 n+1 READ WITH COUNTER . IH CY7C09079V/89V/99V CY7C09179V/89V/99V t HAD t HCN Q n+1 n+2 COUNTER HOLD READ WITH COUNTER t t SAD HAD t t SCN HCN Q n+2 READ COUNTER HOLD WITH COUNTER Q n+3 Q n+3 Page ...

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... The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06043 Rev n n+1 n+1 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = V IL CY7C09079V/89V/99V CY7C09179V/89V/99V [30, 31 n+2 n n+2 n+3 WRITE WITH COUNTER . IH A n+4 n+4 ...

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... HRST CNTRST t SD DATA IN DATA OUT COUNTER RESET Notes: 32 33. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06043 Rev. *A [19, 26, 32, 33 WRITE READ ADDRESS 0 ADDRESS 0 CY7C09079V/89V/99V CY7C09179V/89V/99V n READ READ ADDRESS 1 ADDRESS n Page n ...

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... CNTRST I/O Mode Reset out( out( out( Increment out(n+ CY7C09079V/89V/99V CY7C09179V/89V/99V –I/O Operation 9 [37] Deselected [37] Deselected Write [37] Read Outputs Disabled Operation Counter Reset to Address 0 Load Address Load into Counter Hold External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation Page ...

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... CY7C09099V-7AC 9 CY7C09099V-9AC CY7C09099V-9AI 12 CY7C09099V-12AC 32K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09179V-6AC [1] 7.5 CY7C09179V-7AC 9 CY7C09179V-9C 12 CY7C09179V-12AC 64K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09189V-6AC [1] 7.5 CY7C09189V-7AC 9 CY7C09189V-9AC 12 CY7C09189V-12AC 128K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 ...

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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C09079V/89V/99V CY7C09179V/89V/99V 51-85048-B Page ...

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... Document Title: CY7C09079V/89V/99V, CY7C09179V/89V/99V 3.3V 32K/64K/128K x 8/9Synchronous Dual Port Static RAM Document Number: 38-06043 Issue REV. ECN NO. Date ** 110191 09/29/01 *A 122293 12/27/02 Document #: 38-06043 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00667 to 38-06043 RBI Power up requirements added to Operating Conditions Information ...