CY7C1315JV18-300BZC Cypress Semiconductor Corp, CY7C1315JV18-300BZC Datasheet
CY7C1315JV18-300BZC
Specifications of CY7C1315JV18-300BZC
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CY7C1315JV18-300BZC Summary of contents
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... DDR interfaces. Each address location is associated with four 8-bit words (CY7C1311JV18) or 9-bit words (CY7C1911JV18) or 18-bit words (CY7C1313JV18) or 36-bit words (CY7C1315JV18) that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks (K and K and C ...
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... Logic Block Diagram (CY7C1911JV18 [8:0] 19 Address A (18:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [0] Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Write Write Write Write Address Reg Reg Reg Reg Register Control Logic Read Data Reg Reg. Reg. 16 Reg. Write Write Write ...
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... Logic Block Diagram (CY7C1313JV18 [17:0] 18 Address A (17:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Logic Block Diagram (CY7C1315JV18 [35:0] 17 Address A (16:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Write ...
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... Pin Configuration The pin configuration for CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 follow NC/72M DOFF V V REF DDQ TDO TCK NC/72M DOFF V V REF DDQ TDO TCK A Note 1. NC/36M, NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. ...
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... Pin Configuration The pin configuration for CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 follow NC/144M NC/36M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO TCK ...
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... CY7C1311JV18 arrays each of 512K x 9) for CY7C1911JV18, arrays each of 256K x 18) for CY7C1313JV18 and 512K arrays each of 128K x 36) for CY7C1315JV18. Therefore, only 19 address inputs are needed to access the entire memory array of CY7C1311JV18 and CY7C1911JV18, 18 address inputs for CY7C1313JV18 and 17 address inputs for CY7C1315JV18 ...
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... Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Pin Description Switching Characteristics on page 23. Switching Characteristics on page 23. output impedance are set to 0.2 x RQ, where resistor connected [x:0] , which enables the ...
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... Functional Overview The CY7C1311JV18, CY7C1911JV18, CY7C1315JV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port ...
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... All pending transactions (read and write) are completed before the device is deselected. Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Programmable Impedance Connect an external resistor, RQ, between the ZQ pin on the SRAM and V to enable the SRAM to adjust its output driver SS impedance ...
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... MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# Delayed K Delayed 50ohms Truth Table The truth table for CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 follows. Operation K RPS WPS [8] Write Cycle: L-H H Load address on the rising edge of K; write data on two consecutive K and K rising edges. [9] ...
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... Note 10. Is based on a write cycle that was initiated in accordance with the different portions of a write cycle, as long as the setup and hold requirements are achieved. Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 [2, 10] Comments ) are written into the device. [7:0] ) are written into the device. ...
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... Write Cycle Descriptions The write cycle description table for CY7C1315JV18 follows. BWS BWS BWS BWS L– – L– – L– – L– – L– – L– – Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 [2, 10] K Comments – During the data portion of a write sequence, all four bytes (D the device. L– ...
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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Instruction Register Three-bit instructions are serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 16 ...
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... Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 The shifting of data for the SAMPLE and PRELOAD phases occurs concurrently when required, that is, while the data captured is shifted out, the preloaded data is shifted in. ...
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... TAP Controller State Diagram The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 [11] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- EXIT1-DR ...
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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 13. Overshoot: V (AC) < 0.85V (Pulse width less than t IH DDQ 14. All Voltage referenced to Ground. Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 0 Bypass Register Instruction Register ...
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... CS CH 16. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Description [16] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50Ω ...
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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Value CY7C1911JV18 CY7C1313JV18 000 000 00000110100 00000110100 1 1 Description Description CY7C1315JV18 000 Version number. SRAM. 00000110100 Allows unique identification of SRAM vendor. 1 Indicates the presence register. Bit Size ...
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... Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 1H 10D 10C 66 3B 11D 11B 70 ...
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... DDQ DOFF Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 DLL Constraints ■ DLL uses K clock as its synchronizing input. The input has low phase jitter, which is specified as t ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior ...
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... V REF DDQ 21. The operation current is calculated with 50% read cycle and 50% write cycle. Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch-up Current ................................................... > 200 mA Operating Range Range Commercial ...
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... Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V 250Ω, V pulse levels of 0.25V to 1.25V, and output loading of the specified I Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Test Conditions Test Conditions T = 25° MHz ...
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... These parameters are only guaranteed by design and are not tested in production KHKH 26 are specified with a load capacitance (b) of CHZ CLZ 27. At any voltage and temperature t is less than t CHZ Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 Description [24] , BWS ) BWS ) 2 3 [25] [26, 27] ...
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... Outputs are disabled (High-Z) one clock cycle after a NOP. 30. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 [28, 29, 30] WRITE READ ...
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... Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) Ordering Code 300 CY7C1311JV18-300BZC CY7C1911JV18-300BZC CY7C1313JV18-300BZC CY7C1315JV18-300BZC CY7C1311JV18-300BZXC CY7C1911JV18-300BZXC CY7C1313JV18-300BZXC CY7C1315JV18-300BZXC CY7C1311JV18-300BZI CY7C1911JV18-300BZI CY7C1313JV18-300BZI CY7C1315JV18-300BZI CY7C1311JV18-300BZXI CY7C1911JV18-300BZXI ...
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... Package Diagram Figure 6. 165-Ball FBGA ( 1.40 mm), 51-85180 Document Number: 001-12562 Rev. *D CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 51-85180 *B Page [+] Feedback ...
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... Document History Page Document Title: CY7C1311JV18/CY7C1911JV18/CY7C1313JV18/CY7C1315JV18, 18-Mbit QDR Burst Architecture Document Number: 001-12562 ORIG. OF SUBMISSION REVISION ECN CHANGE ** 808457 VKN See ECN *A 1423164 VKN/AESA See ECN *B 2189567 VKN/AESA See ECN *C 2561974 VKN/PYRS 09/04/08 *D 2748221 NJY 08/04/09 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’ ...