ST62T18CB6 STMicroelectronics, ST62T18CB6 Datasheet
ST62T18CB6
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ST62T18CB6 Summary of contents
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MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 20-PIN PACKAGE 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125°C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up ...
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ST62T18C/E18C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 ...
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I/O Port Option Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST62P18C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62T18C and ST62E18C devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which are targeted at low to medium complexity applications. All ST62xx de- vices are based on a building ...
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ST62T18C/E18C INTRODUCTION (Cont’d) OTP and EPROM devices are functionally identi- cal. The ROM based versions offer the same func- tionality selecting as ROM options the options de- fined in the programmable option byte of the OTP/ EPROM versions.OTP devices offer ...
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PIN DESCRIPTIONS V and V . Power is supplied to the MCU via DD SS these two pins the power connection and the ground connection. SS OSCin and OSCout. These pins are internally connected ...
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ST62T18C/E18C 1.3 MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Briefly, Program space contains user program code ...
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... U.V. erasure that also results into the whole EPROM context erasure. Note: Once the Readout Protection is activated longer possible, even for STMicroelectronics, to gain access to the Program memory contents. Returned parts with a protection set can therefore not be accepted. ...
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ST62T18C/E18C MEMORY MAP (Cont’d) 1.3.3 Data Space Data Space accommodates all the data necessary for processing the user program. This space com- prises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants ...
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MEMORY MAP (Cont’d) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes locat- ed anywhere in program memory, between ad- ...
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ST62T18C/E18C MEMORY MAP (Cont’d) 1.3.6 Data RAM Bank Register (DRBR) Address: CBh — Write only DRBR4 DRBR3 Bit 7-5 = These bits are not used Bit 4 - DRBR4. This bit, when set, selects RAM Page ...
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PROGRAMMING MODES 1.4.1 Option Bytes The two Option Bytes allow configuration capabili the MCUs. Option byte’s content is automati- cally read, and the selected options enabled, when the chip reset is activated. It can only be accessed ...
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ST62T18C/E18C 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and Pe- ...
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CPU REGISTERS (Cont’d) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the ad- dress of ...
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ST62T18C/E18C 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ble ...
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CLOCK SYSTEM (Cont’d) Turning on the main oscillator is achieved by re- setting the OSCOFF bit of the A/D Converter Con- trol Register or by resetting the MCU. Restarting the main oscillator implies a delay comprising the oscillator start up ...
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ST62T18C/E18C CLOCK SYSTEM (Cont’d) Figure 9. OSG Filtering Principle (1) (2) (3) (4) (1) Maximum Frequency for the device to work correctly (2) Actual Quartz Crystal Frequency at OSCin pin (3) Noise from OSCin (4) Resulting Internal Frequency Figure 10. ...
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CLOCK SYSTEM (Cont’d) Figure 11. Clock Circuit Block Diagram MAIN OSCILLATOR Figure 12. Maximum Operating Frequency (f Maximum FREQUENCY (MHz 2.5 3 Notes this area, operation is guaranteed at the ...
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ST62T18C/E18C 3.2 RESETS The MCU can be reset in four ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. – by Low Voltage Detection (LVD) 3.2.1 RESET ...
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RESETS (Cont’d) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. ...
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ST62T18C/E18C RESETS (Cont’d) 3.2.6 MCU Initialization Sequence When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (locat program ROM starting at address 0FFEh). A jump to the beginning ...
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RESETS (Cont’d) Table 6. Register Reset Status Register Port Data Registers Port Direction Register Port Option Register Interrupt Option Register TIMER Status/Control AR TIMER Mode/Control Register AR TIMER Status/Control Register 0 AR TIMER Status/Control Register ...
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ST62T18C/E18C 3.3 DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this ...
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DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register This register is set to 0FEh on Reset: bit ...
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ST62T18C/E18C DIGITAL WATCHDOG (Cont’d) 3.3.1 Digital Watchdog Register (DWDR) Address: 0D8h — Read/Write Reset status: 1111 1110 Bit Watchdog Control bit If the hardware option is selected, this bit is ...
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DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 instructions ...
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ST62T18C/E18C 3.4 IINTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction to the ...
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INTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context ...
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ST62T18C/E18C INTERRUPTS (Cont’d) 3.4.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be ...
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INTERRUPTS (Cont’d) Interrupt Polarity Register (IPR) Address: DAh — Read/Write PortD In conjunction with I/O register ESB bit, the polarity of I/O pins triggered interrupts can be selected by setting accordingly the Interrupt Polarity Register ...
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ST62T18C/E18C INTERRUPTS (Cont’d) Figure 21. Interrupt Block Diagram NMI FROM REGISTER PORT A,B,D SINGLE BIT ENABLE PBE V DD IPR Bit 1 PORT A Bits IPR Bit 0 PBE PORT B Bits IPR Bit 3 PORT D PBE Bits ARTIMER ...
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POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following ...
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ST62T18C/E18C POWER SAVING MODE (Cont’d) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the restart ...
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ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt – Input with ...
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ST62T18C/E18C I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters (OR). ...
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I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe transitions are illustrated ...
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ST62T18C/E18C I/O PORTS (Cont’d) Table 13. I/O Port configuration for the ST62T18C/E18C MODE AVAILABLE ON PA1-PA5 Input PB4-PB6 (Reset state if PORT PULL option disabled) PD4-PD7 PA1-PA5 Input PB4-PB6 with pull up (Reset state if PORT PULL option enabled) PD4-PD7 ...
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I/O PORTS (Cont’d) 4.1.3 ARTimer alternate functions When the PWMOE bit of ARMC register is low, the PA2/ARTIMout pin is configured as any standard pin of port B through the port registers. PA2/ARTIMout pin must be configured as output push-pull ...
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ST62T18C/E18C I/O PORTS (Cont’d) Figure 24. Peripheral Interface Configuration of UART and AR Timer PD4/RXD1 PD5/TXD1 PA3/ARTIMin PA2/ARTIMout 40/ PID DR PID DR 0 MUX 1 PID DR PID 1 MUX 0 DR RXD UART IARTOE TXD ...
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I/O PORTS (Cont’d) 4.1.5 I/O Port Option Registers ORA/B/D (CCh PA, CDh PB, CFh PD) Read/Write 7 Px7 Px6 Px5 Px4 Px3 Bit 7-0 = Px7 - Px0: Port A, B, and D Option Reg- ister bits. 4.1.6 I/O Port ...
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ST62T18C/E18C 4.2 TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 The peripheral may be configured in three different operating modes. Figure 25 shows ...
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TIMER (Cont’d) 4.2.1 Timer Operating Modes There are three operating modes, which are se- lected by the TOUT and DOUT bits (see TSCR register). These three modes correspond to the two clocks which can be connected to the 7-bit prescaler ...
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ST62T18C/E18C TIMER (Cont’d) 4.2.3 Application Notes TMZ is set when the counter reaches zero; howev- er, it may also be set by writing 00h in the TCR register or by setting bit 7 of the TSCR register. The TMZ bit ...
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AUTO-RELOAD TIMER The Auto-Reload Timer (AR Timer) on-chip pe- ripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as f external ...
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ST62T18C/E18C AUTO-RELOAD TIMER (Cont’d) Figure 27. AR Timer Block Diagram f INT M f 7-Bit /3 U INT AR PRESCALER X PS0-PS2 CC0-CC1 PA3/ ARTIMin SL0-SL1 EF SYNCHRO 46/82 46 DATA BUS 8 AR COMPARE REGISTER 8 CPF COMPARE 8 ...
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AUTO-RELOAD TIMER (Cont’d) It should be noted that the reload values will also affect the value and the resolution of the duty cycle of PWM output signal. To obtain a signal on ARTI- Mout, the contents of the ARCP register ...
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ST62T18C/E18C AUTO-RELOAD TIMER (Cont’d) Capture Mode with PWM Generation. In this mode, the AR counter operates as a free running 8-bit counter fed by the prescaler output. The counter is incremented on every clock rising edge. An 8-bit capture operation ...
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AUTO-RELOAD TIMER (Cont’d) 4.3.3 AR Timer Registers AR Mode Control Register (ARMC) Address: E5h — Read/Write Reset status: 00h 7 TCLD TEN PWMOE EIE CPIE The AR Mode Control Register ARMC is used to program the different operating modes of ...
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ST62T18C/E18C AUTO-RELOAD TIMER (Cont’d) AR Status Control Register 1(ARSC1) Address: E7h — Read/Write 7 PS2 PS1 PS0 D4 SL1 Bist 7-5 = PS2-PS0: Prescaler Division Selection Bits 2-0. These bits determine the Prescaler divi- sion ratio. The prescaler itself is ...
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A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device depend- ent), offering 8-bit resolution with a typical conver- sion time of ...
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ST62T18C/E18C A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. Such switching will affect the sup- ...
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(Universal Asynchronous Receiver/Transmitter) The UART provides the basic hardware for asyn- chronous serial communication which, combined with an appropriate software routine, gives a serial interface providing communication with common baud rates (up to 76,800 Baud ...
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ST62T18C/E18C (Cont’d) 4.5.2 Clock Generation The UART contains a built-in divider of the MCU internal clock for most common Baud Rates as shown in Table 19. Other baud rate values can be calculated from the chosen ...
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(Cont’d) 4.5.4 Data Reception The UART continuously looks for a falling edge on the input pin whenever a transmission is not ac- tive. Once an edge is detected it waits 1 bit time (8 states) to ...
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ST62T18C/E18C (Cont’d) UART Control Register (UARTCR) Address: D7h, Read/Write 7 RXRDY TXMT RXIEN TXIEN BR2 Bit 7 = RXRDY. Receiver Ready . This flag be- comes active as soon as a complete byte has been received ...
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SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core ...
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ST62T18C/E18C 5.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control ...
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INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either a data space ...
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ST62T18C/E18C INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either sets ...
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Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6 LOW 0 1 0000 0001 HI 2 JRNZ 4 CALL abc 0000 1 pcr 2 ext 1 2 JRNZ 4 ...
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ST62T18C/E18C Opcode Map Summary (Continued) LOW 8 9 1000 1001 HI 2 JRNZ abc 0000 1 pcr 2 ext 1 2 JRNZ abc 0001 1 pcr 2 ext 1 2 ...
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ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the ...
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ST62T18C/E18C 6.2 RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A V Operating Supply Voltage Oscillator Frequency OSC I Pin Injection Current (positive) INJ+ I Pin Injection Current (negative) V INJ- Notes: 1. Care must be taken ...
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DC ELECTRICAL CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins (1) Hysteresis Voltage V Hys All Input ...
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ST62T18C/E18C DC ELECTRICAL CHARACTERISTICS (Cont’ -40 to +85°C unless otherwise specified)) A Symbol Parameter V LVD Threshold in power- LVD threshold in powerdown dn Low Level Output Voltage All Output pins V OL Low Level Output ...
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A/D CONVERTER CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter Res Resolution (1) (2) A Total Accuracy TOT t Conversion Time C ZIR Zero Input Reading FSR Full Scale Reading Analog Input Current During AD ...
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ST62T18C/E18C Figure frequency versus Vcc . 10 1 0.1 3 3.5 This curves represents typical variations and is given for guidance only Figure 36. LVD thresholds versus temperature 4.2 4.1 4 3.9 3.8 3.7 3.6 -40°C This ...
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Figure 37. Idd WAIT versus Vcc at 8 Mhz for OTP devices 1.2 1 0.8 0.6 0.4 0 This curves represents typical variations and is given for guidance only Figure 38. Idd STOP versus Vcc for OTP devices ...
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ST62T18C/E18C Figure 40. Idd WAIT versus Vcc at 8Mhz for ROM devices 0.8 0.6 0.4 0 This curves represents typical variations and is given for guidance only Figure 41. Idd RUN versus Vcc at 8 Mhz for ROM ...
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Figure 43. Vol versus Iol on all I/O port at T=25° This curves represents typical variations and is given for guidance only Figure 44. Vol versus Iol for High sink (20mA) I/Oports at ...
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ST62T18C/E18C Figure 46. Voh versus Ioh on all I/O port at 25° Figure 47. Voh versus Ioh on all I/O port at Vdd= This curves represents ...
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GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 48. 20-Pin Plastic Dual In-Line Package, 300-mil Width Figure 49. 20-Pin Ceramic Side-Brazed Dual In-Line Package CDIP20W ...
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... Figure 50. 20-Pin Plastic Small Outline Package, 300-mil Width THERMAL CHARACTERISTIC Symbol Parameter RthJA Thermal Resistance 7.2 ORDERING INFORMATION Table 26. OTP/EPROM VERSION ORDERING INFORMATION Sales Type Memory (Bytes) ST62E18CF1 7948 (EPROM) ST62T18CB6 ST62T18CM6 ST62T18CB3 ST62T18CM3 74/ 45× Test Conditions Min. PDIP20 ...
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MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 20-PIN PACKAGE 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125°C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up ...
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... MCU. The listing is then returned to the customer who must thoroughly check, com- plete, sign and return it to STMicroelectronics. The signed listing forms a part of the contractual agree- ment for the production of the specific customer MCU ...
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MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 20-PIN PACKAGE 3.0 to 6.0V Supply Operating Range 8 MHz Maximum Clock Frequency -40 to +125°C Operating Temperature Range Run, Wait and Stop Modes 5 Interrupt Vectors Look-up ...
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ST6218C 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6218C is mask programmed ROM version of ST62T18C OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP ...
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... Sales Type ST6218CB1/XXX ST6218CB6/XXX ST6218CB3/XXX ST6218CM1/XXX ST6218CM6/XXX ST6218CM3/XXX STMicroelectronics. The signed listing forms a part of the contractual agreement for the creation of the specific customer mask. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. Table 1. ROM Memory Map for ST6218C ...
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... Enabled [ ] Enabled [ ] Quartz crystal / Ceramic resonator [ ] RC network FASTROM Enabled ROM Enabled Fuse is blown by STMicroelectronics [ ] Fuse can be blown by the customer [ ] Disabled [ ] Enabled [ ] Enabled [ ] 10-bit [ ] Enabled [ ] Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SUMMARY OF CHANGES Rev. Changed section 4.1.3 on page 39. Changed Figure 24 on page Changed Figure 27 on page 2.6 Changed section 1.1 on page 76. Changed Figure 48 on page 73 Changed option list (page 80 Main ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics ...