IC EEPROM 1KBIT 3MHZ 8DIP

 

93C46C-E/P

Manufacturer Part Number93C46C-E/P
DescriptionIC EEPROM 1KBIT 3MHZ 8DIP
ManufacturerMicrochip Technology
93C46C-E/P datasheets

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Specifications of 93C46C-E/P

Format - MemoryEEPROMs - SerialMemory TypeEEPROM
Memory Size1K (128 x 8 or 64 x 16)Speed3MHz
InterfaceMicrowire, 3-Wire SerialVoltage - Supply4.5 V ~ 5.5 V
Operating Temperature-40°C ~ 125°CPackage / Case8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.9
Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA46A/B/C and 93LC46A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C46A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction,
but the chip must be in the EWEN status.
FIGURE 2-10:
WRAL TIMING FOR 93AA AND 93LC DEVICES
CS
CLK
0
DI
1
0
0
High-Z
DO
must be 4.5V for proper operation of WRAL.
V
CC
FIGURE 2-11:
WRAL TIMING FOR 93C DEVICES
CS
CLK
0
DI
1
0
0
High-Z
DO
 2010 Microchip Technology Inc.
The DO pin indicates the Ready/
device if CS is brought high after a minimum of 250 ns
low (T
).
CSL
Note:
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/
must be 4.5V for proper operation of WRAL.
V
CC
T
1
x
•••
Dx
•••
D0
x
T
1
x
•••
Dx
•••
D0
x
status of the
Busy
Busy
status from DO.
CSL
T
T
SV
CZ
Busy
Ready
H
-Z
IGH
T
WL
CSL
T
T
SV
CZ
Busy
Ready
H
-Z
IGH
T
WL
DS21749H-page 11