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93C46C-E/P
93C46C-E/P | |
|---|---|
| Manufacturer Part Number | 93C46C-E/P |
| Description | IC EEPROM 1KBIT 3MHZ 8DIP |
| Manufacturer | Microchip Technology |
| 93C46C-E/P datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Specifications of 93C46C-E/P | |||
|---|---|---|---|
| Format - Memory | EEPROMs - Serial | Memory Type | EEPROM |
| Memory Size | 1K (128 x 8 or 64 x 16) | Speed | 3MHz |
| Interface | Microwire, 3-Wire Serial | Voltage - Supply | 4.5 V ~ 5.5 V |
| Operating Temperature | -40°C ~ 125°C | Package / Case | 8-DIP (0.300", 7.62mm) |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
PrevNext
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.5
Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
FIGURE 2-3:
ERAL TIMING FOR 93AA AND 93LC DEVICES
CS
CLK
DI
1
0
0
High-Z
DO
must be 4.5V for proper operation of ERAL.
V
CC
FIGURE 2-4:
ERAL TIMING FOR 93C DEVICES
CS
CLK
DI
1
0
0
High-Z
DO
DS21749H-page 8
The DO pin indicates the Ready/
device if CS is brought high after a minimum of 250 ns
low (T
).
CSL
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/
must be 4.5V for proper operation of ERAL.
V
CC
T
CSL
1
0
x
•••
x
T
CSL
•••
1
0
x
x
T
status of the
Busy
Busy
status from DO.
Check Status
T
T
SV
CZ
Busy
Ready
High-Z
T
EC
Check Status
T
T
SV
CZ
Busy
Ready
High-Z
EC
2010 Microchip Technology Inc.
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