IC EEPROM 1KBIT 3MHZ 8DIP

 

93C46C-E/P

Manufacturer Part Number93C46C-E/P
DescriptionIC EEPROM 1KBIT 3MHZ 8DIP
ManufacturerMicrochip Technology
93C46C-E/P datasheets

Availability: By request

International delivery:

Warranty: 60 days

Shipping & payment terms

Added to cart

 

Specifications of 93C46C-E/P

Format - MemoryEEPROMs - SerialMemory TypeEEPROM
Memory Size1K (128 x 8 or 64 x 16)Speed3MHz
InterfaceMicrowire, 3-Wire SerialVoltage - Supply4.5 V ~ 5.5 V
Operating Temperature-40°C ~ 125°CPackage / Case8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Page 8/34

Download datasheet (713Kb)Embed
PrevNext
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.5
Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical ‘1’ state. The ERAL cycle
is identical to the erase cycle, except for the different
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS, except on
‘93C’ devices where the rising edge of CLK before the
last data bit initiates the write cycle. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
FIGURE 2-3:
ERAL TIMING FOR 93AA AND 93LC DEVICES
CS
CLK
DI
1
0
0
High-Z
DO
must be 4.5V for proper operation of ERAL.
V
CC
FIGURE 2-4:
ERAL TIMING FOR 93C DEVICES
CS
CLK
DI
1
0
0
High-Z
DO
DS21749H-page 8
The DO pin indicates the Ready/
device if CS is brought high after a minimum of 250 ns
low (T
).
CSL
Note:
After the ERAL command is complete,
issuing a Start bit and then taking CS low
will clear the Ready/
must be 4.5V for proper operation of ERAL.
V
CC
T
CSL
1
0
x
•••
x
T
CSL
•••
1
0
x
x
T
status of the
Busy
Busy
status from DO.
Check Status
T
T
SV
CZ
Busy
Ready
High-Z
T
EC
Check Status
T
T
SV
CZ
Busy
Ready
High-Z
EC
 2010 Microchip Technology Inc.