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- Integrated Circuits (ICs)/
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93C46C-E/P
93C46C-E/P | |
|---|---|
| Manufacturer Part Number | 93C46C-E/P |
| Description | IC EEPROM 1KBIT 3MHZ 8DIP |
| Manufacturer | Microchip Technology |
| 93C46C-E/P datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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- If you still have any questions - please contact us
Specifications of 93C46C-E/P | |||
|---|---|---|---|
| Format - Memory | EEPROMs - Serial | Memory Type | EEPROM |
| Memory Size | 1K (128 x 8 or 64 x 16) | Speed | 3MHz |
| Interface | Microwire, 3-Wire Serial | Voltage - Supply | 4.5 V ~ 5.5 V |
| Operating Temperature | -40°C ~ 125°C | Package / Case | 8-DIP (0.300", 7.62mm) |
| Lead Free Status / RoHS Status | Lead free / RoHS Compliant | ||
PrevNext
93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C
2.6
Erase/Write Disable and Enable
(EWDS/EWEN)
The 93XX46A/B/C powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be preceded
by an Erase/Write Enable (EWEN) instruction. Once the
EWEN instruction is executed, programming remains
FIGURE 2-5:
EWDS TIMING
CS
CLK
DI
1
0
0
FIGURE 2-6:
EWEN TIMING
CS
CLK
1
0
0
DI
2.7
Read
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (if ORG pin is low or A-version
devices) or 16-bit (if ORG pin is high or B-version
devices) output string.
FIGURE 2-7:
READ TIMING
CS
CLK
DI
A
1
1
0
N
High-Z
DO
2010 Microchip Technology Inc.
enabled until an EWDS instruction is executed or Vcc is
removed from the device.
To protect against accidental data disturbance, the EWDS
instruction can be used to disable all erase/write functions
and should follow all programming operations. Execution
of a READ instruction is independent of both the EWEN and
EWDS instructions.
•••
0
0
x
x
•••
1
1
x
x
The output data bits will toggle on the rising edge of the
CLK and are stable after the specified time delay (T
Sequential read is possible when CS is held high. The
memory data will automatically cycle to the next register
and output sequentially.
•••
A0
Dx
D0
Dx
0
•••
•••
T
CSL
T
CSL
).
PD
D0
Dx
D0
•••
DS21749H-page 9
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93C46C-E/SN |
IC EEPROM 1KBIT 3MHZ 8SOIC | Microchip Technology |
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93C46CT-E/ST |
IC EEPROM 1KBIT 3MHZ 8TSSOP | Microchip Technology |
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93C46C-E/MS |
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|
