93C66A-E/MS Microchip Technology, 93C66A-E/MS Datasheet - Page 6

• Manufacturer Part Number: 93C66A-E/MS
• Description: IC EEPROM 4KBIT 2MHZ 8MSOP
• Manufacturer: Microchip Technology

Specifications of 93C66A-E/MS

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 2MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
2.0
When the ORG pin is connected to V
nization is selected. When it is connected to ground,
the
addresses and write data are clocked into the DI pin on
the rising edge of the clock (CLK). The DO pin is
normally held in a High-Z state except when reading
data from the device, or when checking the Ready/
Busy
Ready/
Write operation by polling the DO pin; DO low indicates
that programming is still in progress, while DO high
indicates the device is ready. DO will enter the High-Z
state on the falling edge of CS.
2.1
The Start bit is detected by the device if CS and DI are
both high with respect to the positive edge of CLK for
the first time.
Before a Start condition is detected, CS, CLK and DI
may change in any combination (except to that of a
Start condition), without resulting in any device
operation (Read, Write, Erase, EWEN, EWDS, ERAL
or WRAL). As soon as CS is high, the device is no
longer in Standby mode.
An instruction following a Start condition will only be
executed if the required opcode, address and data bits
for any particular instruction are clocked in.
DS21795D-page 6
Note:
(x8)
status during a programming operation. The
Busy
FUNCTIONAL DESCRIPTION
Start Condition
When preparing to transmit an instruction,
either the CLK or DI signal levels must be
at a logic low as CS is toggled active high.
organization
status can be verified during an Erase/
is
selected.
CC
, the (x16) orga-
Instructions,
2.2
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the read operation, if A0 is a logic high
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin. In order to
limit this current, a resistor should be connected
between DI and DO.
2.3
All modes of operation are inhibited when V
a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices
or 3.8V for ‘93C’ devices.
The EWEN and EWDS commands give additional
protection against accidentally programming during
normal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before the initial ERASE or WRITE instruction
can be executed.
Block Diagram
ORG*
DI
CLK
Note:
CS
*ORG input is not available on A/B devices
Data In/Data Out (DI/DO)
Data Protection
Data Register
V
For added protection, an EWDS command
should be performed after every write
operation.
CC
Memory
Register
Decode
Array
Clock
Mode
Logic
V
SS
© 2008 Microchip Technology Inc.
Address
Decoder
Address
Counter
Output
Buffer
CC
is below
DO