24LCS21AT/SN Microchip Technology, 24LCS21AT/SN Datasheet

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24LCS21AT/SN

Manufacturer Part Number
24LCS21AT/SN
Description
IC EEPROM 1KBIT 400KHZ 8SOIC
Manufacturer
Microchip Technology
Datasheet

Specifications of 24LCS21AT/SN

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
1K (128 x 8)
Speed
100kHz, 400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
24LCS21AT/SN
Manufacturer:
NEC
Quantity:
300
Part Number:
24LCS21AT/SN
Manufacturer:
MICROCHIPS
Quantity:
3 850
DDC is a trademark of the Video Electronics Standards Assoc.
I
Features:
• Single Supply with Operation Down to 2.5V
• Completely Implements DDC1™/DDC2™ Inter-
• Low-Power CMOS Technology:
• 2-Wire Serial Interface Bus, I
• 100 kHz (2.5V) and 400 kHz (5V) Compatibility
• Self-Timed Write Cycle (including Auto-Erase)
• Hardware Write-Protect Pin
• Page Write Buffer for up to Eight Bytes
• 1,000,000 Erase/Write Cycles Ensured
• Data Retention > 200 years
• ESD Protection > 4000V
• 8-pin PDIP and SOIC Package
• Available for Extended Temperature Ranges:
• Pb-Free and RoHS Compliant
Description:
The Microchip Technology Inc. 24LCS21A is a
128 x 8-bit dual-mode Electrically Erasable PROM.
This device is designed for use in applications
requiring storage and serial transmission of configura-
tion and control information. Two modes of operation
have been implemented: Transmit-Only mode and
Bidirectional mode. Upon power-up, the device will be
in the Transmit-Only mode, sending a serial bit stream
of the memory array from 00h to 7Fh, clocked by the
VCLK pin. A valid high-to-low transition on the SCL
pin will cause the device to enter the Transition mode
and look for a valid control byte on the I
detects a valid control byte from the master, it will
switch into Bidirectional mode, with byte selectable
read/write capability of the memory array using SCL.
If no control byte is received, the device will revert to
the Transmit-Only mode after it receives 128 consec-
utive VCLK pulses while the SCL pin is idle. The
24LCS21A also enables the user to write-protect the
entire memory array using its write-protect pin. The
24LCS21A is available in a standard 8-pin PDIP and
SOIC package in industrial temperature range.
© 2007 Microchip Technology Inc.
2
C is a trademark of Philips Corporation.
face for Monitor Identification, Including Recovery
to DDC1
- 1 mA active current, typical
- 10 μA standby current, typical at 5.5V
- Industrial (I):
1K 2.5V Dual Mode I
-40°C to +70°C
2
C™ Compatible
2
C bus. If it
2
C
Package Types
Block Diagram
Pin Function Table
SDA
PDIP
V
V
SOIC
CC
Control
SS
Serial EEPROM
VCLK
Logic
Name
VCLK
I/O
SDA
SCL
V
V
WP
NC
SCL
SS
CC
Vss
24LCS21A
WP
NC
NC
Vss
WP
NC
NC
Control
Memory
Logic
WP
1
2
3
4
1
2
3
4
Write-Protect (active low)
Ground
Serial Address/Data I/O
Serial Clock (Bidirectional mode)
Serial Clock (Transmit-Only mode)
+2.5V to 5.5V Power Supply
No Connection
XDEC
Function
8
7
6
5
8
7
6
5
DS21161H-page 1
Vcc
VCLK
SCL
SDA
Page Latches
R/W Control
HV Generator
Sense AMP
Vcc
VCLK
SCL
SDA
EEPROM
Array
YDEC

Related parts for 24LCS21AT/SN

24LCS21AT/SN Summary of contents

Page 1

... Industrial (I): -40°C to +70°C • Pb-Free and RoHS Compliant Description: The Microchip Technology Inc. 24LCS21A is a 128 x 8-bit dual-mode Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configura- tion and control information. Two modes of operation have been implemented: Transmit-Only mode and Bidirectional mode ...

Page 2

... CC μA I — 30 CCS μA — 100 +1.0V CC Conditions ≥ 2.7V (Note < 2.7V (Note) CC (Note mA 2.5V (Note mA 2. OUT 5.0V (Note 25° MHz A CLK 5.5V, SCL = 400 kHz 3.0V, SDA = SCL = 5.5V, SDA = SCL = CLK SS © 2007 Microchip Technology Inc. ...

Page 3

... This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. © 2007 Microchip Technology Inc. Vcc = 2.5-4.5V Vcc = 4.5 - 5.5V Standard Mode ...

Page 4

... On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the Most Significant bit in address 00h. (Figure 2-2). T VAA Null Bit Bit 1 (MSB) VLOW Bit 7 T VAA VAA Bit 8 Bit © 2007 Microchip Technology Inc. ...

Page 5

... SDA VCLK count = 1 2 VCLK © 2007 Microchip Technology Inc. Once the device has switched into the Bidirectional mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two-wire Bidirectional data transmission protocol (I ...

Page 6

... VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA. 2: The dash box and text “The 24LCS21A and... inside dash box.” are added by Microchip Technology Inc. 3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LCS21A. ...

Page 7

... SCL SDA Start Condition © 2007 Microchip Technology Inc. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation ...

Page 8

... Acknowledge bit if the slave address was true and it is not in a programming mode. Operation Slave Address Read 1010000 Write 1010000 DS21161H-page 8 V HYS STA T T HIGH DAT SU DAT T AA FIGURE 3-7: Start generates R STO Stop STO T BUF CONTROL BYTE ALLOCATION Read/Write R/W A Slave Address © 2007 Microchip Technology Inc. ...

Page 9

... Note, however, that the VCLK is ignored during the self-timed program operation. Changing VCLK from high-to-low during the self-timed program operation will not halt programming of the device. © 2007 Microchip Technology Inc. 24LCS21A 4.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24LCS21A in the same way byte write ...

Page 10

... FIGURE 4-1: BYTE WRITE Bus Activity R Master T SDA Line S Bus Activity VCLK FIGURE 4-2: VCLK WRITE ENABLE TIMING SCL SDA IN VCLK T VHST DS21161H-page 10 Word Control Byte Address STA SU STO S T Data SPVL © 2007 Microchip Technology Inc. ...

Page 11

... FIGURE 5-2: PAGE WRITE S T Bus Activity A Control Master R Byte T SDA Line Bus Activity K VCLK © 2007 Microchip Technology Inc. FIGURE 5-1: Write Command Initiate Write Cycle Send Control Byte Word Data Address Data ( 24LCS21A ACKNOWLEDGE POLLING FLOW Send Send Stop ...

Page 12

... R/W bit set to a one. The 24LCS21A will then issue an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24LCS21A discontinues transmission (Figure 7-2). CURRENT ADDRESS READ Control R O Data n Byte © 2007 Microchip Technology Inc. ...

Page 13

... To provide sequential reads the 24LCS21A contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. © 2007 Microchip Technology Inc Word Control ...

Page 14

... WP This pin is used for flexible write protection of the 24LCS21A. When the last memory location (7Fh) is written with any data, this pin is enabled and determines the write capability of the 24LCS21A (Table 6-1). DS21161H-page 14 © 2007 Microchip Technology Inc. ...

Page 15

... Corrections to Section 1.0, Electrical Characteristics. Revision G Revised Section 8.4; Added On-Line Support page. Revision H Features Section - Add Pb-free and remove Commer- cial Temp; Revised Description; Table 1-1, Remove Commercial Temp, Revised Input/Output conditions; Revise Product ID section. © 2007 Microchip Technology Inc. 24LCS21A DS21161H-page 15 ...

Page 16

... Dual Mode I2C Serial EEPROM 24LCS21AT Dual Mode I2C Serial EEPROM (Tape and Reel) Temperature I = -40°C to +85°C Range: Package Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead DS21161H-page 16 XXX Pattern . © 2007 Microchip Technology Inc. ...

Page 17

... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2007 Microchip Technology Inc. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...

Page 18

... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21161H-page 18 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS21161H © 2007 Microchip Technology Inc. ...

Page 19

... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 20

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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