AD9508/PCBZ Analog Devices, AD9508/PCBZ Datasheet - Page 21

• Manufacturer Part Number: AD9508/PCBZ
• Description: Clock & Timer Development Tools 1
• Manufacturer: Analog Devices
• Type: Clock Buffersr

Specifications of AD9508/PCBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9508
• Frequency: 250 MHz, 1.65 GHz
• Operating Supply Voltage: 6 V
• Description/function: High performance 1
• Interface Type: I2C, SPI, USB
• Factory Pack Quantity: 1

Data Sheet
THEORY OF OPERATION
DETAILED BLOCK DIAGRAM
The
the CLK and CLK pins or a single-ended 1.8 V CMOS clock
applied to the CLK pin. The input clock signal is sent to the clock
distribution section, which has programmable dividers and
phase offset adjustment. The clock distribution section operates
at speeds of up to 1650 MHz.
The divider range under SPI or I
divide-by-1024 and the phase offset adjustment is equipped with
11 bits of resolution. However, in pin programming mode, the
divider range is limited to a maximum divide-by-16 and there is
no phase offset adjustment available.
The outputs can be configured to as many as four LVDS/HSTL
differential outputs or as many as eight 1.8 V CMOS single-
ended outputs. In addition, the output current for the different
outputs is adjustable for output drive strength.
The device can be powered with either a 3.3 V or 2.5 V external
supply; however, the internal supply on the chip runs off an
internal 1.8 V LDO, delivering high performance with minimal
power consumption.
SCLK/SCL/S0
SDIO/SDA/S1
PROG_SEL
AD9508
SDO/S3
IN_SEL
RESET
CS/S2
SYNC
CLK
CLK
S4
S5
accepts either a differential input clock applied to
SDA
SCL
6
INTERFACE
INTERFACE
SPI/I
2
C control ranges from 1 to
SPI
PROG
I
2
2
C
C/PIN_
COARSE
A/D
READ CONTROL
DIGITAL LOGIC
PIN PROGRAM
REGISTERS
REVISION ID
Figure 41. Detailed Block Diagram
AND
Rev. A | Page 21 of 40
SUB LDO
SUB LDO
PROGRAMMING MODE SELECTION
The
strapping option to program the device. The active interface
depends on the logic state of the PROG_SEL pin. See Table 13
for programming mode selections. See the Serial Control Port
and Pin Strapping to Program on Power-Up sections for more
detailed information.
Table 13. SPI/I2C/Pin Serial Port Setup
PROG_SEL
Float
Logic 0
Logic 1
CLOCK INPUT
The IN_SEL pin controls the desired input clock configuration.
When the IN_SEL pin is set for single-ended operation, the
device expects 1.8 V, 2.5 V, or 3.3 V CMOS-compatible logic
levels on the CLK input pin. Bypass the unused CLK pin to
ground with a 0.1 μF capacitor.
When the IN_SEL pin is set for differential input clock mode,
the inputs of the
LDO
LDO
AD9508
supports both SPI and I2C protocols, and a pin
DIVIDER
DIVIDER
DIVIDER
DIVIDER
10-BIT
10-BIT
10-BIT
10-BIT
AD9508
SPI/I²C/Pin
SPI
I²C
Pin programming control
are internally self biased. The internal
11-BIT
11-BIT
11-BIT
11-BIT
∆Φ
∆Φ
∆Φ
∆Φ
LVDS/HSTL/CMOS
OUTPUTS
AD9508
VDD
EXT_CAP0
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
EXT_CAP1
VDD