AD9508/PCBZ Analog Devices, AD9508/PCBZ Datasheet - Page 22

• Manufacturer Part Number: AD9508/PCBZ
• Description: Clock & Timer Development Tools 1
• Manufacturer: Analog Devices
• Type: Clock Buffersr

Specifications of AD9508/PCBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9508
• Frequency: 250 MHz, 1.65 GHz
• Operating Supply Voltage: 6 V
• Description/function: High performance 1
• Interface Type: I2C, SPI, USB
• Factory Pack Quantity: 1

inputs have a resistor divider, which sets the common-mode
level. The complementary input is biased about 30 mV lower
than the true input to avoid oscillations in the event that the
input signal ceases. See Figure 42 for the equivalent differential
input circuit.
The inputs can be ac-coupled or dc-coupled in differential
mode. See Table 14 for input logic compatibility. The user can
supply a single-ended input with the input in differential mode
by ac or dc coupling to one side of the differential input and
bypassing the other input to ground by a capacitor.
Note that jitter performance degrades with low input slew rate,
as shown in Figure 25. See Figure 34 through Figure 37 for
different input clock termination schemes.
CLOCK OUTPUTS
Each channel output driver can be configured for either a
differential LVDS/HSTL output or two single-ended CMOS
outputs. When the LVDS/HSTL driver is enabled, the
corresponding CMOS driver is in tristate. When the CMOS
driver is enabled, the corresponding LVDS/HSTL driver is
powered down and tristated. See Figure 43 and Figure 44 for
the equivalent output stages.
Table 14. CLK and
Supply (V)
3.3
2.5
1.8
3.3
2.5
1.8
1.5
N/A
3.3
2.5
1.8
1
2
AD9508
IN_SEL is set for single-ended CMOS mode.
N/A means not applicable.
1 F
1
1
1
2 F
2
Figure 43. LVDS/HSTL Output Simplified Equivalent Circuit
Figure 42. AD9508 Differential Input Stage
CLK
12.5kΩ
16.5kΩ
Logic
CML
CML
CML
CMOS
CMOS
CMOS
HSTL
LVDS
LVPECL
LVPECL
LVPECL
CLK
A
E
A
V
Differential Input Logic Compatibility
DD
Common Mode (V)
2.9
2.1
1.4
1.65
1.25
0.9
0.75
1.25
2.0
1.2
0.5
OUTx
OUTx
13kΩ
16kΩ
V
CLK
GND
DD
Rev. A | Page 22 of 40
Output Swing (V)
0.8
0.8
0.8
3.3
2.5
1.8
0.75
0.4
0.8
0.8
0.8
In LVDS or HSTL modes, there are register settings to control the
output logic type and current drive strength. The LVDS output
current can be set to the nominal 3.5 mA, additional settings
include 0.5, 0.75, 1.0 (default), and 1.25 multiplied by 3.5 mA.
The HSTL output current can be set to 8 mA (nominal) or
16 mA (double amplitude). For pin programming mode, see the
Pin Strapping to Program on Power-Up section for details and
limitations of the device. Under pin programming mode, the
nominal current is the default setting and is nonadjustable.
When routing single-ended CMOS signals, avoid driving multiple
input receivers with one output. Series termination at the source
is generally required to provide transmission line matching and/or
to reduce current transients at the driver. The value of the series
resistor is dependent on the board design and timing require-
ments (typically 10 Ω to 100 Ω). CMOS outputs are also limited in
terms of the capacitive load or trace length that they can drive.
Typically, trace lengths less than 3 inches are recommended to
preserve signal rise/fall times and signal integrity.
Figure 45. Series Termination of CMOS Output
Figure 44. CMOS Equivalent Output Circuit
AD9508
V
DD
AC-Coupled
Yes
Yes
Yes
Not allowed
Not allowed
Not allowed
Yes
Yes
Yes
Yes
Yes
OUTxA
10Ω
MICROSTRIP
(1.0 INCH)
60.4Ω
V
DD
CMOS
OUTxB
DC-Coupled
Not allowed
Not allowed
Yes
Yes
Yes
Yes
Yes
Yes
Not allowed
Yes
Yes
Data Sheet