AD9508/PCBZ Analog Devices, AD9508/PCBZ Datasheet - Page 25

• Manufacturer Part Number: AD9508/PCBZ
• Description: Clock & Timer Development Tools 1
• Manufacturer: Analog Devices
• Type: Clock Buffersr

Specifications of AD9508/PCBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9508
• Frequency: 250 MHz, 1.65 GHz
• Operating Supply Voltage: 6 V
• Description/function: High performance 1
• Interface Type: I2C, SPI, USB
• Factory Pack Quantity: 1

Data Sheet
PIN STRAPPING TO PROGRAM ON POWER-UP
The PROG_SEL input when set to Logic 1 places the
pin strapping control mode without the need for SPI or I
operations. In this mode, Pin S0 through Pin S5 program the
desired internal divider value and output logic type for each
output or to set the output to a high-Z state.
The maximum divide value is limited to divide-by-16 and phase
offset delay control is not supported in this mode. LVDS and
HSTL logic types are supported in this mode. However, if HSTL
mode is set and the 100 Ω output termination is removed, the
output swings to 1.8 V CMOS logic levels. In this configura-
tion, the differential outputs of the channel selected become two
single-ended CMOS signals. Those outputs maintain a 180° phase
relationship and share the same channel divider value.
Programming individual outputs and the output logic type is
performed by hardwiring specific resistor values to each of the
Table 15. Selection Table for Pin Strapping Control
Programming
Pins
S0
S1
S2
S3
S4
S5
0 = 820 Ω
Pulled to
GND
÷1
÷1
÷1
÷1
HSTL/
HSTL
HSTL/
HSTL
ADC Voltage Level (0 Through 7) vs. Resistor Value vs. Divide Value and Logic Type
1 = 1.8 kΩ
Pulled to
GND
÷2
÷2
÷2
÷2
HSTL/
LVDS
HSTL/
LVDS
2 = 3.9 kΩ
Pulled to
GND
÷3
÷3
÷3
÷3
HSTL/
high-Z
HSTL/
high-Z
3 = 8.2 kΩ
Pulled to
GND
÷4
÷4
÷4
÷4
LVDS/
HSTL
LVDS/
HSTL
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4 = 820 Ω
Pulled to
VDD
÷5
÷5
÷5
÷5
LVDS/
LVDS
LVDS/
LVDS
S0 to S5 pins. The other side of the resistor is then biased to
ground or VDD, depending on the desired settings. The actual
settings are applied after an internal ADC scans each one of the
S0 to S5 pins. An ADC scan is initiated by either the internal
power-on reset when the device is powered up or by toggling
the SYNC pin. If changes are made after the internal power-on
reset, the SYNC pin must be toggled before any new changes are
accepted.
Table 15 depicts all the pin strapping selections available for
each output channel divider value and logic type. The resistors
listed in Table 15 must have 10% or better tolerance.
Note that if all outputs use an output divider value of one and
use either HSTL outputs or 1.8 V CMOS output levels, then the
S0 to S5 pins can be grounded to accomplish that particular
configuration instead of using the 820 Ω resistor.
5 = 1.8 kΩ
Pulled to
VDD
÷6
÷6
÷6
÷6
LVDS/
high-Z
LVDS/
high-Z
6 = 3.9 kΩ
Pulled to
VDD
÷8
÷8
÷8
÷8
High-Z/
HSTL
High-Z/
HSTL
7 = 8.2 kΩ
Pulled to
VDD
÷16
÷16
÷16
÷16
High Z/
high-Z
High-Z/
high-Z
Description
SO is assigned to the
Channel 0 divider ratio only
S1 is assigned to the
Channel 1 divider ratio only
S2 is assigned to the
Channel 2 divider ratio only
S3 is assigned to the
Channel 3 divider ratio only
S4 is assigned to Channel 0
and Channel 1 to select their
output logic types
S5 is assigned to Channel 2
and Channel 3 to select their
output logic types
AD9508