AD9508/PCBZ Analog Devices, AD9508/PCBZ Datasheet - Page 26

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AD9508/PCBZ

Manufacturer Part Number
AD9508/PCBZ
Description
Clock & Timer Development Tools 1
Manufacturer
Analog Devices
Type
Clock Buffersr
Datasheet

Specifications of AD9508/PCBZ

Rohs
yes
Product
Evaluation Boards
Tool Is For Evaluation Of
AD9508
Frequency
250 MHz, 1.65 GHz
Operating Supply Voltage
6 V
Description/function
High performance 1
Interface Type
I2C, SPI, USB
Factory Pack Quantity
1
SERIAL CONTROL PORT
The AD9508 serial control port is a flexible, synchronous serial
communications port that provides a convenient interface to
many industry-standard microcontrollers and microprocessors.
The serial control port is compatible with most synchronous
transfer formats, including I²C, Motorola SPI, and Intel SSR
protocols. The serial control port allows read/write access to the
AD9508
In SPI mode, single- or multiple-byte transfers are supported.
The SPI port configuration is programmable via Register 0x00.
This register is integrated into the SPI control logic rather than
in the register map and it is distinct from the I
SPI/I²C PORT SELECTION
The AD9508 has two serial interfaces, SPI and I²C. Users can
select either SPI or I²C depending on the state of the PROG_SEL
pin. In I²C operation, four different I²C slave address (seven bits
wide) settings are available, see Table 16. The five MSBs of the
slave address are hardware coded as 11011 and Pin S4 and Pin
S5 program the two LSBs.
Table 16. Serial Port Mode Selection
S4
Low
Low
High
High
SPI SERIAL PORT OPERATION
Pin Descriptions
The SCLK (serial clock) pin serves as the serial shift clock. This
pin is an input. SCLK synchronizes serial control port read and
write operations. The rising edge SCLK registers write data bits,
and the falling edge registers read data bits. The SCLK pin
supports a maximum clock rate of 40 MHz.
The SDIO (serial data input/output) pin is a dual-purpose pin
and acts either as an input only (unidirectional mode) or as both
an input and an output (bidirectional mode). The
default SPI mode is bidirectional.
The SDO (serial data output) pin is useful only in unidirectional
I/O mode. It serves as the data output pin for read operations.
The
and write operations. This pin is internally connected to a 30 kΩ
pull-up resistor. When
a high impedance state.
AD9508
CS
E E
A A
(chip select) pin is an active low control that gates read
register map.
S5
Low
High
Low
High
CS
A A
E E
A A
is high, the SDO and SDIO pins enter
Address
I²C, 1101100
I²C, 1101101
I²C, 1101110
I²C, 1101111
2
C Register 0x00.
AD9508
Rev. A | Page 26 of 40
SPI Mode Operation
The SPI port supports both 3-wire (bidirectional) and 4-wire
(unidirectional) hardware configurations and both MSB first
and LSB first data formats. Both the hardware configuration
and data format features are programmable. By default, the
AD9508
bidirectional is the default mode is so that the user can continue
to write to the device (if it is wired for unidirectional operation)
to switch to unidirectional mode.
Assertion (active low) of the
operation to the
bytes or fewer (excluding the instruction word), the device
supports the
be temporarily deasserted on any byte boundary, allowing time
for the system controller to process the next byte. However,
can be deasserted on byte boundaries only; this applies to both
the instruction and data portions of the transfer.
During stall high periods, the serial control port state machine
enters a wait state until all data is sent. If the system controller
decides to abort a transfer midstream, the state machine must be
reset either by completing the transfer or by asserting the
pin for at least one complete SCLK cycle (but less than eight
SCLK cycles). Deasserting the
terminates the serial transfer and flushes the buffer.
In streaming mode (see Table 17), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented.
at the end of the last byte that is transferred, thereby ending the
stream mode.
Table 17. Byte Transfer Count
W1
0
0
1
1
Communication Cycle—Instruction Plus Data
The SPI protocol consists of a two part communication cycle.
The first part is a 16-bit instruction word that is coincident with
the first 16 SCLK rising edges and a payload. The instruction
word provides the
regarding the payload. The instruction word includes the R/
bit that indicates the direction of the payload transfer; that is, a
read or write operation. The instruction word also indicates the
number of bytes in the payload and the starting register address
of the first payload byte.
uses the bidirectional MSB first mode. The reason that
W0
0
1
0
1
CS
A A
E E
A A
stalled high mode. In this mode, the
AD9508
AD9508
SPI port. For data transfers of three
Bytes to Transfer
1
2
3
Streaming mode
serial control port with information
CS
A A
CS
A A
E E
A A
pin initiates a write or read
E E
A A
pin on a nonbyte boundary
CS
A A
E E
A A
must be deasserted
Data Sheet
CS
A A
E E
A A
pin can
A A
CS
CS
A A
W
A A
E E
A A
E E
A A
E E
A A

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