AD9508/PCBZ Analog Devices, AD9508/PCBZ Datasheet - Page 31

• Manufacturer Part Number: AD9508/PCBZ
• Description: Clock & Timer Development Tools 1
• Manufacturer: Analog Devices
• Type: Clock Buffersr

Specifications of AD9508/PCBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9508
• Frequency: 250 MHz, 1.65 GHz
• Operating Supply Voltage: 6 V
• Description/function: High performance 1
• Interface Type: I2C, SPI, USB
• Factory Pack Quantity: 1

Data Sheet
Data Transfer Format
Write byte format: The write byte protocol writes a register address to the RAM, starting from the specified RAM address.
S
Send byte format: The send byte protocol sets up the register address for subsequent reads.
S
Receive byte format: The receive byte protocol reads the data byte(s) from RAM, starting from the current address.
S
Read byte format: This is the combined format of the send byte and the receive byte.
S
I²C Serial Port Timing
Table 22. I2C Timing Definitions
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
SCL
BUF
HD; STA
SU; STA
SU; STO
HD; DAT
SU; DAT
LOW
HIGH
R
F
SP
Slave
Address
Slave
Address
Slave Address
Slave Address
SDA
SDA
SCL
SCL
t
F
S
S
W
A
W
A
E
E
t
HD; STA
A
t
Description
Serial clock
Bus free time between stop and start conditions
Repeated hold time start condition
Repeated start condition setup time
Stop condition setup time
Data hold time
Date setup time
SCL clock low period
SCL clock high period
Minimum/maximum receive SCL and SDA rise time
Minimum/maximum receive SCL and SDA fall time
Pulse width of voltage spikes that must be suppressed by the input filter
LOW
A
1
RAM
Address
High Byte
RAM Address
High Byte
W
A
R
t
E
R
2
t
HD; DAT
A
Figure 58. Data Transfer Process (Master Read Mode, Two-Byte Transfer)
A
t
SU; DAT
A
3 TO 7
RAM Address High Byte
RAM Data 0
t
RAM
Address
Low Byte
HIGH
A
t
F
Figure 59. I²C Serial Port Timing
8
RAM Address
Low Byte
MASTER RECEIVER
Rev. A | Page 31 of 40
ACK FROM
t
SU; STA
A
9
Sr
A
Slave
Address
Sr
1
RAM Data 1
A
t
HD; STA
2
RAM
Data 0
A
R
A
RAM Address Low Byte
3 TO 7
RAM
Data 0
A
t
SP
t
A
SU; STO
RAM
Data 1
A
8
RAM Data 2
MASTER RECEIVER
NACK FROM
t
R
RAM
Data 1
P
A
9
t
BUF
A
RAM
Data 2
10
S
P
RAM
Data 2
AD9508
A
A
A
E
A
A
A
E
P
P
P
P