AD9508/PCBZ Analog Devices, AD9508/PCBZ Datasheet - Page 32

• Manufacturer Part Number: AD9508/PCBZ
• Description: Clock & Timer Development Tools 1
• Manufacturer: Analog Devices
• Type: Clock Buffersr

Specifications of AD9508/PCBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9508
• Frequency: 250 MHz, 1.65 GHz
• Operating Supply Voltage: 6 V
• Description/function: High performance 1
• Interface Type: I2C, SPI, USB
• Factory Pack Quantity: 1

REGISTER MAP
Register addresses that are not listed in Table 23 are unused, and writing to those registers has no effect. The user should write the default
value to sections of registers marked reserved.
The abbreviation, R, in the optional (Opt) column in Table 23 means read only and NS means that the value does not change during a soft
reset. Note that the default column is represented by Def.
Table 23. Register Map
Reg
Addr
(Hex)
Serial Control Port Configuration and Part Identification
0x00
0x00
0x0A
0x0B
0x0C
0x0D
Chip Level Functions
0x12
0x13
0x14
OUT0 Functions
0x15
0x16
0x17
0x18
0x19
0x1A
OUT1 Functions
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
OUT2 Functions
0x21
0x22
0x23
0x24
0x25
0x26
OUT3 Functions
0x27
0x28
0x29
0x2A
0x2B
0x2C
AD9508
Opt
NS
NS
R, NS
R, NS
R, NS
R,NS
NS
Name
SPI control
I²C control
Silicon rev
Reserved
Part ID
Part ID
Reserved
Sleep
SYNC_BAR
OUT0
Divide
Ratio[9:0]
OUT0
Phase[9:0]
OUT0 Driver
OUT0 CMOS
OUT1
Divide
Ratio[9:0]
OUT1
Phase[9:0]
OUT1 Driver
OUT1 CMOS
OUT2
Divide
Ratio[9:0]
OUT2
Phase[9:0]
OUT2 Driver
OUT2 CMOS
OUT3
Divide
Ratio[9:0]
OUT3
Phase[9:0]
OUT3 Driver
OUT3 CMOS
D7
SDO enable
PD_0
PD_1
PD_2
EN_CMOS_2P
PD_3
EN_CMOS_3P
EN_CMOS_0P
EN_CMOS_1P
Reserved
D6
LSB first/
increment
address
SYNCMASK0
SYNCMASK2
SYNCMASK3
SYNCMASK1
Reserved
CMOS_0P_PHASE[1:0]
CMOS_1P_PHASE[1:0]
CMOS_2P_PHASE[1:0]
CMOS_3P_PHASE[1:0]
D5
Soft reset
Soft reset
Reserved
Reserved
Reserved
Reserved
OUT0 Driver Phase[1:0]
OUT1 Driver Phase[1:0]
OUT2 Driver Phase[1:0]
OUT3 Driver Phase[1:0]
Rev. A | Page 32 of 40
Reserved
Reserved
Reserved
Reserved
Clock Part Family ID[15:8]
Reserved
Clock Part Family ID[7:0]
D4
Sleep
EN_CMOS_0N
EN_CMOS_1N
EN_CMOS_2N
EN_CMOS_3N
OUT0 Divide Ratio[7:0]
OUT1 Divide Ratio[7:0]
OUT2 Divide Ratio[7:0]
OUT3 Divide Ratio[7:0]
Silicon Revision[7:0]
OUT2 Phase [7:0]
OUT0 Phase[7:0]
OUT1 Phase[7:0]
OUT3 Phase[7:0]
Reserved
Reserved
Reserved
Reserved
D3
CMOS_0N_PHASE[1:0]
CMOS_1N_PHASE[1:0]
CMOS_2N_PHASE[1:0]
CMOS_3N_PHASE[1:0]
OUT0 Mode[2:0]
OUT1 Mode[2:0]
OUT2 Mode[2:0]
OUT3 Mode[2:0]
D2
Soft reset
Soft reset
Reserved
OUT0 Phase[10:8]
OUT1 Phase[10:8]
OUT2 Phase[10:8]
OUT3 Phase[10:8]
D1
LSB first/
increment
address
OUT0 Divide Ratio[9:8]
OUT1 Divide Ratio[9:8]
OUT2 Divide Ratio[9:8]
OUT3 Divide Ratio[9:8]
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet
D0
SYNC_BAR
Reserved
Reserved
Reserved
SDO enable
Reserved
Def
00
00
00
00
05
00
02
00
01
00
00
00
00
14
00
00
00
00
00
14
00
00
00
00
00
14
00
00
00
00
00
14
00