AD9508/PCBZ Analog Devices, AD9508/PCBZ Datasheet - Page 34

• Manufacturer Part Number: AD9508/PCBZ
• Description: Clock & Timer Development Tools 1
• Manufacturer: Analog Devices
• Type: Clock Buffersr

Specifications of AD9508/PCBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9508
• Frequency: 250 MHz, 1.65 GHz
• Operating Supply Voltage: 6 V
• Description/function: High performance 1
• Interface Type: I2C, SPI, USB
• Factory Pack Quantity: 1

OUT0 FUNCTIONS (REGISTER 0x15 TO REGISTER 0x1A)
Table 27. Divide Ratio and Phase
Address
0x15
0x16
0x17
0x18
Table 28. Output Driver, Power Down, and Sync
Address
0x19
0x1A
AD9508
Bits
[7:0]
[7:2]
[1:0]
[7:0]
[7:3]
[2:0]
Bits
7
6
[5:4]
[3:1]
0
7
[6:5]
4
[3:2]
[1:0]
Bit Name
OUT0 Divide Ratio[7:0]
Reserved
OUT0 Divide Ratio[9:8]
OUT0 Phase[7:0]
Reserved
OUT0 Phase[10:8]
Bit Name
PD_0
SYNCMASK0
OUT0 Driver Phase[1:0]
OUT0 Mode[2:0]
Reserved
EN_CMOS_0P
CMOS_0P_PHASE[1:0]
EN_CMOS_0N
CMOS_0N_PHASE[1:0]
Reserved
Description
Channel 0 divide ratio, Bits[7:0]
0x00 = default
Channel 0 divide ratio, Bits[9:8]
Channel 0 divider phase, Bits[7:0]
0x00 = default
Channel 0 divider phase, Bits[9:8]
Description
Channel 0 power down
Setting this bit masks Channel 0 from the output sync function
0 = Channel 0 is synchronized during output sync (default)
1 = Channel 0 is excluded from an output sync
These bits determine the phase of the OUT0 driver
00 = force high
01 = noninverting (default)
10 = inverting
11 = force low
These bits determine the OUT0 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0b = default
Setting this bit enables the OUT0P CMOS driver
0 = disables the OUT0P CMOS driver (default)
1 = enables the OUT0P CMOS driver
These bits determine the phase of the OUT0P CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
Setting this bit enables the OUT0N CMOS driver
0 = disables the OUT0N CMOS driver (default)
1 = enables the OUT0N CMOS driver
These bits determine the phase of the OUT0N CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
00b = default
Rev. A | Page 34 of 40
Data Sheet