AD9508/PCBZ Analog Devices, AD9508/PCBZ Datasheet - Page 36

• Manufacturer Part Number: AD9508/PCBZ
• Description: Clock & Timer Development Tools 1
• Manufacturer: Analog Devices
• Type: Clock Buffersr

Specifications of AD9508/PCBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9508
• Frequency: 250 MHz, 1.65 GHz
• Operating Supply Voltage: 6 V
• Description/function: High performance 1
• Interface Type: I2C, SPI, USB
• Factory Pack Quantity: 1

OUT2 FUNCTIONS (REGISTER 0x21 TO REGISTER 0x26)
Table 31. Divide Ratio and Phase
Address
0x21
0x22
0x23
0x24
Table 32. Output Driver, Power Down, and Sync
Address
0x25
0x26
AD9508
Bits
[7:0]
[7:2]
[1:0]
[7:0]
[7:3]
[2:0]
Bits
7
6
[5:4]
[3:1]
0
7
[6:5]
4
[3:2]
[1:0]
Bit Name
OUT2 Divide Ratio[7:0]
Reserved
OUT2 Divide Ratio[9:8]
OUT2 Phase[7:0]
Reserved
OUT2 Phase[10:8]
Bit Name
PD_2
SYNCMASK2
OUT2 Driver Phase[1:0]
OUT2 Mode[2:0]
Reserved
EN_CMOS_2P
CMOS_2P_PHASE[1:0]
EN_CMOS_2N
CMOS_2N_PHASE[1:0]
Reserved
Description
Channel 2 divide ratio, Bits[7:0]
0x00 = default
Channel 2 divide ratio, Bits[9:8]
Channel 2 divider phase, Bits[7:0]
0x00 = default
Channel 2 divider phase, Bits[9:8]
Description
Channel 2 power-down
Setting this bit masks OUT2 from the output sync function
0 = Channel 2 is synchronized during output sync (default)
1 = Channel 2 is excluded from an output sync
These bits determine the phase of the OUT2 driver
00 = force high
01 = noninverting (default)
10 = inverting
11 = force low
These bits determine the OUT2 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0b = default
Setting this bit enables the OUT2P CMOS driver
0 = disables the OUT2P CMOS driver (default)
1 = enables OUT2P CMOS driver
These bits determine the phase of the OUT2P CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
Setting this bit enables the OUT2N CMOS driver
0 = disables the OUT2N CMOS driver (default)
1 = enables OUT2N CMOS driver
These bits determine the phase of the OUT2N CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
00b = default
Rev. A | Page 36 of 40
Data Sheet