EVAL-AD5259DBZ Analog Devices, EVAL-AD5259DBZ Datasheet
EVAL-AD5259DBZ
Specifications of EVAL-AD5259DBZ
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EVAL-AD5259DBZ Summary of contents
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... Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...
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... Read Modes ................................................................................. 17 Store/Restore Modes .................................................................. 17 Tolerance Readback Modes ...................................................... 18 ESD Protection of Digital Pins and Resistor Terminals ........ 19 Power-Up Sequence ................................................................... 19 Layout and Power Supply Bypassing ....................................... 19 Multiple Devices on One Bus ................................................... 19 Evaluation Board ........................................................................ 19 Display Applications ...................................................................... 20 Circuitry ...................................................................................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 22 7/05—Rev Rev. A Added 10-Lead LFCSP ...................................................... Universal Changes to Features Section and General Description Section ...
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Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS ± 10 ± 10 LOGIC Table 1. Parameter DC CHARACTERISTICS: RHEOSTAT MODE Resistor Differential Nonlinearity 5 kΩ 10 kΩ 50 kΩ/100 kΩ Resistor Integral ...
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AD5259 Parameter DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Leakage Current SDA, AD0, AD1 SCL – Logic High SCL – Logic Low Input Capacitance POWER SUPPLIES Power Supply Range Positive Supply Current Logic Supply Logic Supply Current ...
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Data Sheet TIMING CHARACTERISTICS ± 10 ± 10 LOGIC Table 2. Parameter INTERFACE TIMING 1 CHARACTERISTICS SCL Clock Frequency t Bus Free Time Between Stop BUF ...
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AD5259 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter GND DD LOGIC GND MAX 1 Pulsed Continuous Digital Inputs and Output ...
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Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin Mnemonic ADO 3 AD1 4 SDA 5 SCL 6 V LOGIC 7 GND EPAD W A ...
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AD5259 TYPICAL PERFORMANCE CHARACTERISTICS 5 kΩ +25°C; unless otherwise noted. DD LOGIC AB A 1.5 1.3 2.7V 1.1 0.9 0.7 0.5 0.3 0.1 –0.1 –0.3 5.5V –0 ...
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Data Sheet 0.5 0.4 0.3 0.2 0.1 –40°C 0 –0.1 –0.2 –0.3 –0.4 –0 128 160 CODE (Decimal) Figure 12. R-INL vs. Code vs. Temperature 0.5 0.4 0.3 T 0.2 0.1 0 –0 +25°C ...
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AD5259 400 100kΩ 300 50kΩ 200 10kΩ 100 0 –100 –200 –300 5kΩ –400 –500 –600 128 CODE (Decimal) Figure 18. Rheostat Mode Tempco (Δ 10kΩ 20 100kΩ ...
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Data Sheet – – – – – – – –48 –54 –60 1k 10k FREQUENCY (Hz) Figure 24. Gain vs. Frequency vs. Code, ...
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AD5259 1µs/DIV Figure 30. Midscale Glitch, Code 0×7F to 0× SCL 2 Figure 31. Large Signal Settling Time Rev Page Data Sheet W 200ns/DIV ...
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Data Sheet TEST CIRCUITS Figure 32 through Figure 37 illustrate the test circuits that define the test conditions used in the product Specifications tables DUT 1LSB = V+/ Figure 32. Test Circuit ...
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AD5259 THEORY OF OPERATION The AD5259 is a 256-position digitally-controlled variable resistor (VR) device. EEPROM is pre-loaded at midscale from the factory, and initial power-up is, accordingly, at midscale. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance (R ) ...
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Data Sheet I 2 C-COMPATIBLE INTERFACE The master initiates data transfer by establishing a start condi- tion, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 4). The next byte is the ...
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AD5259 I 2 C-COMPATIBLE FORMAT The following generic, write, read, and store/restore control registers for the AD5259 all refer to the device addresses listed in Table 5; the mode/condition reference key (S, P, SA, MA, NA and ...
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Data Sheet READ MODES Read modes are referred to as traditional because the first two bytes for all three cases are dummy bytes, which function to place the pointer towards the correct register; this is the reason for the repeat ...
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AD5259 TOLERANCE READBACK MODES Table 15. Traditional Readback of Tolerance (Individually) 7-Bit Device Address S (See Table Slave Address Byte Instruction Byte 7-Bit Device Address S (See ...
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... Table 5). This allows up to four devices on the bus to be written to or read from independently. before applying any EVALUATION BOARD An evaluation board, with all necessary software, is available are powered LOGIC to program the AD5259 from any PC running Windows® 98/ 2000/ XP. The graphical user interface, as shown in Figure 45, ...
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AD5259 DISPLAY APPLICATIONS CIRCUITRY A special feature of the AD5259 is its unique separation of the V and V supply pins. The separation provides greater LOGIC DD flexibility in applications that do not always provide needed supply voltages. In particular, ...
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Data Sheet OUTLINE DIMENSIONS IDENTIFIER PIN 1 INDEX AREA 0.80 0.75 0.70 SEATING PLANE 3.10 3.00 2.90 5. 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.15 0.23 ...
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... AD5259BRMZ50- AD5259BCPZ50- AD5259BRMZ100 100 k AD5259BRMZ100-R7 100 k AD5259BCPZ100-R7 100 k EVAL-AD5259DBZ RoHS Compliant Part. 2 The evaluation board is shipped with the 10 kΩ R Package Description Temperature –40°C to +125°C 10-Lead MSOP –40°C to +125°C 10-Lead MSOP –40°C to +125°C 10-Lead LFCSP_WD – ...
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Data Sheet NOTES Rev Page AD5259 ...
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... AD5259 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. D05026-0-10/12(C) Rev Page Data Sheet ...