AT26DF321-SU Atmel, AT26DF321-SU Datasheet

IC FLASH 32MBIT 66MHZ 8SOIC

AT26DF321-SU

Manufacturer Part Number
AT26DF321-SU
Description
IC FLASH 32MBIT 66MHZ 8SOIC
Manufacturer
Atmel
Datasheet

Specifications of AT26DF321-SU

Format - Memory
FLASH
Memory Type
DataFLASH
Memory Size
32M (16384 pages x 256 Bytes)
Speed
66MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
AT26DF321-SU
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Features
1. Description
The AT26DF321 is a serial interface Flash memory device designed for use in a wide
variety of high-volume consumer based applications in which program code is shad-
owed from Flash memory into embedded or external RAM for execution. The flexible
erase architecture of the AT26DF321, with its erase granularity as small as 4-Kbytes,
makes it ideal for data storage as well, eliminating the need for additional data storage
EEPROM devices.
The physical sectoring and the erase block sizes of the AT26DF321 have been opti-
mized to meet the needs of today's code and data storage applications. By optimizing
the size of the physical sectors and erase blocks, the memory space can be used
much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused
memory space that occurs with large sectored and large block erase Flash memory
devices can be greatly reduced. This increased memory space efficiency allows addi-
tional code routines and data storage segments to be added while still maintaining the
same overall device density.
Single 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
66 MHz Maximum Clock Frequency
Flexible, Uniform Erase Architecture
Individual Sector Protection with Global Protect/Unprotect Feature
Hardware Controlled Locking of Protected Sectors
Flexible Programming
Automatic Checking and Reporting of Erase/Program Failures
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– Supports SPI Modes 0 and 3
– 4-Kbyte Blocks
– 32-Kbyte Blocks
– 64-Kbyte Blocks
– Full Chip Erase
– Sixty-Four 64-Kbyte Physical Sectors
– Byte/Page Program (1 to 256 Bytes)
– 7 mA Active Read Current (Typical)
– 4 µA Deep Power-Down Current (Typical)
– 8-lead SOIC (208-mil wide)
– 16-lead SOIC (300-mil wide)
32-megabit
2.7-volt Only
Serial Firmware
DataFlash
Memory
AT26DF321
For New
Designs Use
AT25DF321A
3633F–DFLASH–5/7/08
®

Related parts for AT26DF321-SU

AT26DF321-SU Summary of contents

Page 1

... SOIC (208-mil wide) – 16-lead SOIC (300-mil wide) 1. Description The AT26DF321 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shad- owed from Flash memory into embedded or external RAM for execution. The flexible ...

Page 2

... Specifically designed for use in 3-volt systems, the AT26DF321 supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. ...

Page 3

... WP 4. Memory Array To provide the greatest flexibility, the memory array of the AT26DF321 can be erased in four lev- els of granularity including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations ...

Page 4

... Sector Protection Block Erase Function (D8h Command) (52h Command) 64KB 64KB (Sector 63) 64KB 64KB (Sector 62) 64KB 64KB (Sector 0) AT26DF321 4 Block Erase Detail 32KB 4KB Block Address Block Erase Block Erase Range (20h Command) 3FFFFFh – 3FF000h 4KB 4KB 3FEFFFh – 3FE000h 3FDFFFh – ...

Page 5

... SPI Master. All opcode, address, and data bytes are transferred with the most significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT26DF321 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted) ...

Page 6

... Protect Sector Unprotect Sector Global Protect/Unprotect Read Sector Protection Registers Status Register Commands Read Status Register Write Status Register Miscellaneous Commands Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down AT26DF321 6 Opcode Address Bytes 0Bh 0000 1011 3 03h 0000 0011 3 20h ...

Page 7

... MSB HIGH-IMPEDANCE SO Figure 7-2. Read Array – 03h Opcode CS SCK SI SO 3633F–DFLASH–5/7/ ADDRESS BITS A23- MSB MSB OPCODE ADDRESS BITS A23- MSB MSB HIGH-IMPEDANCE AT26DF321 DON'T CARE DATA BYTE MSB MSB DATA BYTE MSB MSB . The 03h SCK . RDLF D 7 ...

Page 8

... The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly programming error arises, it will be indicated by the EPE bit in the Status Register. AT26DF321 8 time to determine if the data bytes have finished programming ...

Page 9

... CS pin is deas- serted; otherwise, the device will abort the operation and no erase operation will be performed. 3633F–DFLASH–5/7/ OPCODE ADDRESS BITS A23- MSB ADDRESS BITS A23-A0 DATA IN BYTE MSB MSB AT26DF321 DATA MSB DATA IN BYTE MSB . BLKE D 9 ...

Page 10

... While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput recommended that the Status Regis- ter be polled rather than waiting the t AT26DF321 10 time to determine if the device has finished erasing. At ...

Page 11

... Status Register will be set to a logical “1”. The complete opcode must be clocked into the device before the CS pin is deasserted; otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. 3633F–DFLASH–5/7/08 Chip Erase SCK OPCODE MSB HIGH-IMPEDANCE SO Write Enable SCK OPCODE MSB HIGH-IMPEDANCE SO AT26DF321 ...

Page 12

... Any additional data clocked into the device will be ignored. When the CS pin is deas- serted, the Sector Protection Register corresponding to the physical sector addressed by A23- A0 will be set to the logical “1” state, and the sector itself will then be protected from program AT26DF321 12 Write Disable ...

Page 13

... If the Sector Protection Registers are locked, then any attempts to Protect Sector SCK OPCODE MSB HIGH-IMPEDANCE SO for more details). If the Sector Protection Registers are locked, then any attempts to AT26DF321 “Status Register Commands” ADDRESS BITS A23- MSB Table 9-1 on page 12 “ ...

Page 14

... Status Register. Conversely, to per- form a Global Unprotect, the same WP and SPRL conditions must be met but the system must write a logical “0” to bits and 2 of the Status Register. necessary for a Global Protect or Global Unprotect to be performed. AT26DF321 14 Unprotect Sector CS ...

Page 15

... Global Protect/Unprotect will not occur. However, the SPRL bit can be changed back from a 1 since the WP pin is HIGH. To perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from AT26DF321 New SPRL Value ...

Page 16

... In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bit in the Status Register can be read to determine if all, some, or none of the sectors are software protected (please refer to AT26DF321 16 for details on the Status Register format and what values can be Read Sector Protection Register – Output Data ...

Page 17

... Global Protect or Global Unprotect at the same time by writing the appropriate values into bits and 2 of the Status Register. 3633F–DFLASH–5/7/08 Read Sector Protection Register OPCODE ADDRESS BITS A23- MSB MSB HIGH-IMPEDANCE AT26DF321 DATA BYTE MSB , the SPRL bit MSB 17 ...

Page 18

... The tables below detail the various protection and locking states of the device. Table 9-4. WP (Don't Care) Note: Table 9- AT26DF321 18 Software Protection Register States Sector Protection Register ( “n” represents a sector number Hardware and Software Locking SPRL Locking SPRL Change Allowed 0 Can be modified from ...

Page 19

... Some sectors are software protected. Read individual 01 Sector Protection Registers to determine which R sectors are protected. 10 Reserved for future use. All sectors are software protected (all Sector 11 Protection Registers are 1 – default). 0 Device is not write enabled (default Device is write enabled. 0 Device is ready Device is busy with an internal operation. AT26DF321 19 ...

Page 20

... Protect Sector, Unprotect Sector, or Write Status Register commands. The WEL bit defaults to the logical “0” state after a device power-up or reset. In addition, the WEL bit will be reset to the logical “0” state automati- cally under the following conditions: AT26DF321 20 3633F–DFLASH–5/7/08 ...

Page 21

... Write Status Register command was executed (the prior state of the SPRL bit) will determine whether or not a Global Protect or Global Unprotect will be perfomed. Please refer to the “Global Protect/Unprotect” section on 3633F–DFLASH–5/7/ OPCODE MSB STATUS REGISTER DATA HIGH-IMPEDANCE MSB page 14 for more details. AT26DF321 STATUS REGISTER DATA MSB MSB Table 10-2). Any addi- 21 ...

Page 22

... Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. AT26DF321 22 Write Status Register Format Bit 6 ...

Page 23

... OPCODE SI 9Fh HIGH-IMPEDANCE 1Fh MANUFACTURER ID Note: Each transition shown for SI and SO represents one byte (8 bits) AT26DF321 Hex Bit 0 Value Details 1Fh JEDEC Code: 0001 1111 (1Fh for Atmel) 1 Family Code: 010 (AT25/26DFxxx series) 47h Density Code: 00111 (32-Mbit) 1 Sub Code: 000 (Standard series) ...

Page 24

... The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-Down mode. Figure 11-2. Deep Power-Down AT26DF321 ...

Page 25

... Deep Power-Down mode. Figure 11-3. Resume from Deep Power-Down 3633F–DFLASH–5/7/08 and return to the standby mode. After the device RDPD SCK OPCODE MSB HIGH-IMPEDANCE SO Active Current I CC Deep Power-Down Mode Current AT26DF321 t RDPD 7 1 Standby Mode Current 25 ...

Page 26

... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT26DF321 -40C to +85C 2.7V to 3.6V Min Typ Max 25 ...

Page 27

... Write Status Register Time WRSR Notes: 1. Not 100% tested (value guaranteed by design and characterization). 3633F–DFLASH–5/7/08 Min 6.8 6.8 0.1 0 100 Min Typ 1.5 6 4-Kbyte 50 32-Kbyte 350 64-Kbyte 600 36 AT26DF321 Max Units 66 MHz 33 MHz ns ns V/ns V/ µs 3 µs Max Units 5 ...

Page 28

... Power-Up Conditions Parameter Minimum V to Chip Select Low Time CC Power-up Device Delay Before Program or Erase Allowed Power-On Reset Voltage 12.7 Input Test Waveforms and Measurement Levels 12.8 Output Test Load AT26DF321 28 2.4V AC DRIVING 1.5V LEVELS 0.45V < (10 DEVICE UNDER ...

Page 29

... Figure 13-3. WP Timing for Write Status Register Command When SPRL = WPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER OPCODE HIGH-IMPEDANCE SO 3633F–DFLASH–5/7/08 t CSLH t t SCKH SCKL t DH LSB WPH LSB OF WRITE STATUS REGISTER DATA BYTE AT26DF321 t CSH t CSHH t CSHS MSB SCKH SCKL DIS MSB MSB OF NEXT OPCODE 29 ...

Page 30

... Ordering Information 14.1 Green Package Options (Pb/Halide-free/RoHS Compliant) f (MHz) Ordering Code SCK 66 AT26DF321-SU 66 AT26DF321-S3U 8S2 8-lead, 0.208" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 16S 16-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) AT26DF321 30 Package 8S2 16S ...

Page 31

... TOP VIEW TOP VIEW SIDE VIEW SIDE VIEW TITLE 8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ) AT26DF321 θ θ END VIEW END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A 1.70 2.16 A1 0.05 ...

Page 32

... Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side the length of the terminal for soldering to a substrate. 2325 Orchard Parkway San Jose, CA 95131 R AT26DF321 TITLE 16S, 16-lead, 0.300" ...

Page 33

... Changed description of bit 5 in Table 10-1 undefined. Removed MLF package offerings. Added 8-lead SOIC (200-mil wide) package. Changed ordering code for 16-lead SOIC from AT26DF321-SU to AT26DF321-S3U. Added errata regarding Chip Erase. Removed “Preliminary” from datasheet. Added information regarding EPE bit. - Added text to “ ...

Page 34

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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