AT25DF641-S3H-T Atmel, AT25DF641-S3H-T Datasheet
AT25DF641-S3H-T
Specifications of AT25DF641-S3H-T
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AT25DF641-S3H-T Summary of contents
Page 1
... Complies with Full Industrial Temperature Range • Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options 16-Lead SOIC (300-mil wide) 8-Contact Very Thin DFN (6 x 8mm) 64-Mbit, 2.7V Minimum Serial Peripheral Interface Serial Flash Memory Atmel AT25DF641 3680F–DFLASH–4/10 ...
Page 2
... EEPROM devices. The physical sectoring and the erase block sizes of the AT25DF641 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently ...
Page 3
... However recommended that the pin also be externally connected to V 3680F–DFLASH–4/10 CS pin selects the device. When the CS pin is required to start an operation, and a low- pin controls the hardware locking feature of the WP whenever possible. CC Atmel AT25DF641 Asserted Type State CS pin is Low Input − Input − ...
Page 4
... HOLD SCK GND (SIO) Atmel AT25DF641 4 pin is used to temporarily pause serial communication without HOLD pin is asserted, transitions on the HOLD pin also be externally connected to pin is used to supply the source voltage to the CC voltages may produce spurious results and should not be CC Figure 1-2. ...
Page 5
... Block Diagram Figure 2-1. Block Diagram CS INTERFACE SCK CONTROL SI (SIO) AND LOGIC SO (SOI) WP HOLD 3680F–DFLASH–4/10 CONTROL AND PROTECTION LOGIC Y-DECODER X-DECODER Atmel AT25DF641 I/O BUFFERS AND LATCHES SRAM DATA BUFFER Y-GATING FLASH MEMORY ARRAY 5 ...
Page 6
... AT25DF641 can be erased in four levels of Page Program Detail 1-256 Byte Page Program Page Address (02h Command) 256 Bytes 7FFFFFh – 7FFF00h 256 Bytes 7FFEFFh– 7FFE00h 256 Bytes 7FFDFFh – ...
Page 7
... All opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the Opcodes not supported by the AT25DF641 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation ( deasserted and then reasserted) ...
Page 8
... Read OTP Security Register Status Register Commands Read Status Register Write Status Register Byte 1 Write Status Register Byte 2 Miscellaneous Commands Reset Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down Atmel AT25DF641 8 Clock Opcode Frequency 1Bh 0001 1011 Up to 75MHz 0Bh 0000 1011 ...
Page 9
... The 1Bh opcode allows the highest read performance RDLF should be reserved to systems employing the RapidS protocol. CLK CS pin must first be asserted and the appropriate opcode (1Bh, 0Bh ADDR BITS A23- Atmel AT25DF641 ; however, use of the 1Bh MAX DON'T CAR E DON'T CAR ...
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... Figure 6-2. Read Array - 0Bh Opcode SCK OP C ODE HIG H-IMP E DANC E SO Figure 6-3. Read Array - 03h Opcode SCK HIG H-IMP E DANC E SO Atmel AT25DF641 ADDR ITS A23- ODE ADDR A23- DON DATA DAT 3680F–DFLASH–4/10 ...
Page 11
... Figure 6-4. Dual-Output Read Array SCK HIG H-IMP E DANC E SO 3680F–DFLASH–4/ ODE ADDR ITS A23- Atmel AT25DF641 pin must first be asserted and the opcode of 3Bh must OUT P UT DON DAT RDDO 44 ...
Page 12
... WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program properly programming error arises, it will be indicated by the EPE bit in the Status Register Atmel AT25DF641 pin must be deasserted on even byte boundaries (multiples of eight bits) ...
Page 13
... SOI and SI pins, respectively. The sequence would continue with each byte of data being input after every four clock cycles. Like the standard Byte/Page Program command, all data clocked into the device is stored in an internal buffer. 3680F–DFLASH–4/ ADDR A23- ODE ADDR A23- Atmel AT25DF641 DAT DAT DAT ...
Page 14
... If a programming error arises, it will be indicated by the EPE bit in the Status Register. Figure 7-3. Dual-Input Byte Program SCK HIG H-IMP E DANC E SOI Atmel AT25DF641 pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the CS pin being deasserted on uneven byte boundaries ...
Page 15
... ADDR A23- pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must CS pin is deasserted, the device will erase the appropriate block. The erasing of the CS pin being deasserted on uneven byte boundaries, or because a memory Atmel AT25DF641 INP UT INP UT DAT DAT DAT ...
Page 16
... WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. Atmel AT25DF641 16 2 ...
Page 17
... OP C ODE pin must first be asserted and the opcode of B0h must be clocked CS pin is deasserted, the program or erase operation currently in progress will be . The Program Suspend (PS) bit or the Erase Suspend (ES) bit in the Status SUSP Atmel AT25DF641 CS CS pin is deasserted, and the pin 17 ...
Page 18
... Protect Sector operation, then the device will simply ignore the opcode and no operation will be performed. The state of the WEL bit in the Status Register, as well as the SPRL (Sector Protection Registers Locked) and SLE (Sector Lockdown Enabled) bits, will not be affected. Atmel AT25DF641 18 3680F–DFLASH–4/10 ...
Page 19
... Read Status Register Write Status Register (All Opcodes) Miscellaneous Commands Reset Read Manufacturer and Device ID Deep Power-Down Resume from Deep Power-Down 3680F–DFLASH–4/10 Atmel AT25DF641 Operation During Operation During Program Suspend Erase Suspend Allowed Not Allowed Not Allowed Not Allowed ...
Page 20
... Suspend command will be ignored. Therefore resumed program or erase operation needs to be subsequently suspended again, the system must either wait the entire t command must check the status of the RDY/BSY bit or the appropriate bit in the Status Register to determine if the previously suspended program or erase operation has resumed. Atmel AT25DF641 ...
Page 21
... HIG H-IMP E DANC E SO 3680F–DFLASH–4/ ODE pin must first be asserted and the opcode of 06h must be clocked CS pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The ODE Atmel AT25DF641 CS CS pin is deasserted, and the pin must be 21 ...
Page 22
... Sector is unprotected and can be programmed and erased Sector is protected and cannot be programmed or erased 1 This is the default state Atmel AT25DF641 22 CS pin must first be asserted and the opcode of 04h must be clocked CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. ...
Page 23
... In addition, the WEL bit in the Status Register will be reset back to the logical “0” state. 3680F–DFLASH–4/ ODE ADDR A23- Atmel AT25DF641 CS pin is deasserted, and the pin must pin is 23 ...
Page 24
... Sectors that have been erase or program suspended must remain in the unprotected state Global Protect operation is attempted while a sector is erase or program suspended, the protection operation will abort, the protection states of all sectors in the Flash memory array will not change, and WEL bit in the Status Register will be reset back to a logical “0”. Atmel AT25DF641 ...
Page 25
... Protect/Unprotect will not occur. However, the SPRL bit can be changed back from a 1 since the ↕ perform a Global Protect/Unprotect, the Write Status Register command must be issued again after the SPRL bit has been changed from Atmel AT25DF641 WP pin must be HIGH in order to change ...
Page 26
... In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bits in the Status Register can be read to determine if all, some, or none of the sectors are software protected (refer to “Read Status Register” on page 34 for more details). Atmel AT25DF641 26 pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from , the first byte of data output will not be valid ...
Page 27
... SPRL (Sector Protection Registers WP pin must be asserted and the SPRL bit must be in the WP pin must first be deasserted, and the SPRL bit in the Status Register must be WP pin is permanently connected to V Sector Protection Register ( Atmel AT25DF641 DAT ...
Page 28
... Issuing the Sector Lockdown command to a particular sector address will set the corresponding Sector Lockdown Register to the logical “1” state. Each Sector Lockdown Register can only be set once; therefore, once set to the logical “1” state, a Sector Lockdown Register cannot be reset back to the logical “0” state. Atmel AT25DF641 28 SPRL Change Allowed ...
Page 29
... HIG H-IMP E DANC E SO 3680F–DFLASH–4/ addition, the WEL bit in the Status Register will be reset back to the logical “0” LOCK CS pin must be deasserted on an even byte boundary (multiples of eight ODE ADDR A23- Atmel AT25DF641 ONF IR MAT ION pin has been 29 ...
Page 30
... WEL bit in the Status Register will be reset to a logical “0”; however, the state of the SLE bit will be unchanged. Figure 9-2. Freeze Sector Lockdown State SCK HIG H-IMP E DANC E SO Atmel AT25DF641 30 CS pin must first be asserted and the opcode of 34h must be CS pin must be deasserted on an even byte boundary (multiples of eight bits ...
Page 31
... Atmel and will contain a unique value for each device. The factory programmed data is fixed and cannot be changed. 3680F–DFLASH–4/10 , the first byte of data output will not be valid. Therefore, if operating at clock CLK OPC ODE ADDR BITS A23- Atmel AT25DF641 CS pin must first be asserted DON DATA BYTE ...
Page 32
... For faster throughput recommended that the Status Register be polled rather than waiting the t time to determine if the data bytes have finished programming. At some point before the OTP Security OTPP Register programming completes, the WEL bit in the Status Register will be reset back to the logical “0” state. Atmel AT25DF641 32 Security Register Byte Number . . . ...
Page 33
... Figure 9-5. Read OTP Security Register SCK -IMP E DANC E SO 3680F–DFLASH–4/ ODE ADDR A23- read the OTP Security Register, the MAX ADDR A23- Atmel AT25DF641 DAT DAT pin must first be asserted N DAT ...
Page 34
... Notes: 1. Only bit 7 of Status Register Byte 1 will be modified when using the Write Status Register Byte 1 command 2. R/W = Readable and writeable R = Readable only Atmel AT25DF641 34 CS pin must first be asserted and the opcode of 05h must be clocked into the , the first two bytes of data output from the Status Register will not be valid. ...
Page 35
... Name Type R/W R pin is deasserted. However, if the WP pin will have to first be deasserted. Atmel AT25DF641 Description 0 Reserved for future use. 0 Reserved for future use. 0 Reserved for future use. 0 Reset command is disabled (default). 1 Reset command is enabled. Sector Lockdown and Freeze Sector Lockdown 0 State commands are disabled (default). ...
Page 36
... WEL bit to be reset when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, or Write Status Register command must have been clocked into the device. Atmel AT25DF641 36 WP pin has been asserted or not ...
Page 37
... RDY/BSY bit changes from a logical “1” logical “0”. Figure 10-1. Read Status Register SCK HIG H-IMP E DANC E SO 3680F–DFLASH–4/ OPCODE TATUS R E GIS TE R BYTE Atmel AT25DF641 TATUS R E GIS TATUS R E GIS TE R BYTE 2 BYTE ...
Page 38
... Table 10-3. Write Status Register Byte 1 Format Bit 7 Bit 6 SPRL X Figure 10-2. Write Status Register Byte SCK HIG H-IMP E DANC E SO Atmel AT25DF641 pin is asserted, then the Write Status Register Byte 1 command will be WP pin must be deasserted. Bit 5 Bit 4 Bit 3 Global Protect/Unprotect ...
Page 39
... HIG H-IMP E DANC E SO 3680F–DFLASH–4/10 Bit 5 Bit 4 Bit 3 X RSTE SLE TATUS R E GIS OPCODE BYTE Atmel AT25DF641 CS pin must first be asserted and the opcode of 31h CS pin is deasserted, the RSTE and SLE bits in CS pin is deasserted, and the Bit 2 Bit 1 Bit pin 39 ...
Page 40
... CS the pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no Reset operation will be performed. Figure 11-1. Reset SCK HIG H-IMP E DANC E SO Atmel AT25DF641 40 pin must first be asserted and the opcode of F0h must be clocked into the device OPCODE CONFIR MATION BYTE IN ...
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... Density Code Product Version Code Atmel AT25DF641 Hex Bit 0 Value Details 1Fh JEDEC Code: 0001 1111 (1Fh for Atmel) 1 Family Code: 010 (AT25DF/26DFxxx series) 48h Density Code: 01000 (64-Mbit) 0 Sub Code: 000 (Standard series) 00h Product Version: 00000 (Initial version) 0 ...
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... Figure 11-2. Read Manufacturer and Device SCK OP C ODE HIG H-IMP E DANC E SO Note: Each transition Atmel AT25DF641 48h MANUF shown for SI and SO represents one byte (8-bits 00h 00h NDE INF OR MAT ION ING 3680F–DFLASH–4/10 ...
Page 43
... Any additional data clocked into the device after the opcode will be CS pin is deasserted, and the CS pin is deasserted. In addition, the device will default to the standby mode after ODE Deep P ower-Down Mode C urrent Atmel AT25DF641 CS CS pin, clocking in the opcode of CS pin must be deasserted on 43 ...
Page 44
... Deep Power-Down mode. Figure 11-4. Resume from Deep Power-Down CS SCK HIG H-IMP E DANC Deep P ower-Down Mode C urrent Atmel AT25DF641 44 CS pin must first be asserted and opcode of ABh must be CS pin is deasserted the ...
Page 45
... SCK high pulse, then the Hold CS pin are asserted. HOLD pin is still asserted, then any operation that may have been started will Hold Atmel AT25DF641 HOLD pin will not pause the HOLD pin must be deasserted during the SCK low Hold ...
Page 46
... RapidS and operate at clock frequencies higher than what can be achieved in a viable SPI implementation, a full clock cycle can be used to transmit data back and forth across the serial bus. The Atmel AT25DF641 is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the rising edge of SCK. ...
Page 47
... I = 0mA; OUT Max Max Max CMOS levels CMOS levels OUT I = 1.6mA Min -100 µ Min OH CC Atmel AT25DF641 Ratings” may cause permanent Atmel AT25DF641 -40°C to 85°C 2.7V to 3.6V Min Typ Max Units 0.2V CC µA µ µA µA ...
Page 48
... Reset Time RST Notes: 1. Not 100% tested (value guaranteed by design and characterization) 2. 15pF load at frequencies above 70MHz, 30pF otherwise 3. Only applicable as a constraint for the Write Status Register Byte 1 command when SPRL = 1 Atmel AT25DF641 48 (Slew Rate) ) (Slew Rate (relative to Clock) (relative to Clock) ...
Page 49
... R F 13.9. Output Test Load DEVICE UNDER TEST 15pF (frequencies above 70MHz) or 30pF 3680F–DFLASH–4/10 4-Kbytes 32-Kbytes 64-Kbytes Parameter MEASUREMENT CC LEVEL Atmel AT25DF641 Min Typ Max Units 1.0 3 µs 50 200 250 600 ms 400 950 64 112 sec µ µs ...
Page 50
... AC Waveforms Figure 14-1. Serial Input Timing SCK HIG H-IMP E DANC E SO Figure 14-2. Serial Output Timing CS SCK Figure 14-3. WP Timing for Write Status Register Byte 1 Command When SPRL = SCK ODE HIG H-IMP E DANC E SO Atmel AT25DF641 DAT DIS ODE 3680F–DFLASH–4/10 ...
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... Figure 14-4. HOLD Timing – Serial Input CS SCK HOLD SI HIG H-IMP E DANC E SO Figure 14-5. HOLD Timing – Serial Output CS SCK t HHH HOLD SI SO 3680F–DFLASH–4/ HHH HLS t HLH t HLS t HLH t t HLQZ Atmel AT25DF641 t HHS t HHS HHQX 51 ...
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... Device Density 64 = 64-megabit Interface 1 = Serial 15.2. Green Package Options (Pb/Halide-free/RoHS Compliant) Ordering Code AT25DF641-S3H-B AT25DF641-S3H-T AT25DF641-MWH-Y AT25DF641-MWH-T Note: The shipping carrier option code is not marked on the devices 16S 16-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) 8MW1 8-contact 8mm, Very Thin Dual Flat No Lead Package (VDFN) ...
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... L is the length of the terminal for soldering to a substrate. Package Drawing Contact: packagedrawings@atmel.com 3680F–DFLASH–4/ Top View e D Side View TITLE 16S, 16-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) Atmel AT25DF641 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM A 2.35 – A1 0.10 – ...
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... VDFN Pin Top View E1 8 Pin # Bottom View Package Drawing Contact: packagedrawings@atmel.com Atmel AT25DF641 Pin #1 Option A Chamfer (C 0.30 Option Pin #1 Notch (0.20 R) TITLE 8MW1, 8-pad ( 1.0 mm Body), Thermally Enhanced Plastic Very Thin Dual Flat No Lead Package (VDFN) C Side View ...
Page 55
... Minor text edits throughout document Changed Standby Current values – Increased typical value from 10µA to 25µA – Increased maximum value from 20µA to 35µA Changed minimum Clock High Time and minimum Clock Low Time from 3.7ns to 4.3ns Initial document release Atmel AT25DF641 Comments 55 ...
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