AT45DB321D-TU Atmel, AT45DB321D-TU Datasheet
AT45DB321D-TU
Specifications of AT45DB321D-TU
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AT45DB321D-TU Summary of contents
Page 1
... MHz. Its 34,603,008 bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream ...
Page 2
... To allow for simple in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
Page 3
... Ground: The ground reference for the power supply. GND should be connected to the system GND ground. 3597O–DFLASH–10/09 pin is used to supply the source voltage to the device. CC voltages may produce spurious results and should not be attempted. CC AT45DB321D Asserted State Type Low Input – Input – ...
Page 4
... RDY/BUSY 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB321D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase operations can be performed at the chip, sector, block or page level ...
Page 5
... The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is reached during a 3597O–DFLASH–10/09 AT45DB321D Table 15-1 on page 28 through Table 15-7 on ...
Page 6
... When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred AT45DB321D 6 specification. The Continuous Array Read bypasses both data buffers and leaves the specification ...
Page 7
... A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). 3597O–DFLASH–10/09 specification. The Main Memory Page Read bypasses both data buffers and SCK . The D1H and D3H opcode can be used for lower frequency CAR1 AT45DB321D . CAR2 7 ...
Page 8
... It is necessary that the page in main memory that is being programmed has been previously erased using one of the erase commands (Page Erase or Block Erase). The programming of the page is internally self-timed and should take place in a maximum time of t status register and the RDY/BUSY pin will indicate that the part is busy. AT45DB321D 8 . During this time, EP ...
Page 9
... PA8/ PA7/ PA6/ PA5/ A17 A16 A15 A14 • • • • • • • • • • • • AT45DB321D PA4/ PA3/ PA2/ PA1/ A13 A12 A11 A10 • • • • • • • • • • • • ...
Page 10
... The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. Only those sectors that are not protected or locked down will be erased. Note: AT45DB321D 10 PA8/ PA7/ PA6/ PA5/ ...
Page 11
... Status Register. 3597O–DFLASH–10/09 Chip Erase CS Opcode SI Byte 1 Each transition represents 8 bits 1. Refer to the errata regarding Chip Erase on AT45DB321D Byte 1 Byte 2 Byte 3 C7H 94H 80H Opcode Opcode Opcode Byte 2 ...
Page 12
... Disable Sector Protection commands. If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector pro- tection is desired and if the WP pin is not used. AT45DB321D 12 Byte 1 3DH Enable Sector Protection ...
Page 13
... When the WP pin is deasserted; however, the sector protection WPE 2 Disable Sector Command Protection Command – Issue Command Issue Command X Not Issued Yet or 2 Issue Command – Issue Command AT45DB321D , then the content of the Sector CC time) as long as the Enable Sec- WPD 3 Sector Protection Status X Disabled Disabled – Enabled X Enabled ...
Page 14
... Sector Protection Register.: Table 9-2. Sector Number Protected Unprotected Table 9-3. Sectors 0a, 0b Unprotected Protect Sector 0a (Pages 0-7) Protect Sector 0b (Pages 8-127) Protect Sectors 0a (Pages 0-7), 0b (Pages 8-127) Note: AT45DB321D 14 Sector Protection Register Sector 0 (0a, 0b) 0a (Pages 0-7) Bit (1) 1. The default value for bytes 0 through 63 when shipped from Atmel is 00H don’ ...
Page 15
... Byte 1 3DH Erase Sector Protection Register CS Opcode Opcode SI Byte 1 Byte 2 Each transition represents 8 bits AT45DB321D PE Byte 2 Byte 3 Byte 4 2AH 7FH Opcode Opcode Byte 3 Byte 4 Section 9.1, the Sector Protection Register , during ...
Page 16
... Command Program Sector Protection Register Figure 9-3. Program Sector Protection Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB321D 16 , during which time the Status Register will indicate that the device is busy Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Byte 1 ...
Page 17
... Instead, a combination of temporarily unprotecting individual sectors along with dis- abling sector protection completely will need to be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded. 3597O–DFLASH–10/ Dummy Byte AT45DB321D Byte 1 Byte 2 Byte 3 32H xxH xxH Data Byte ...
Page 18
... Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB321D 18 Byte 1 3DH Opcode Opcode Opcode Address Byte 2 Byte 3 Byte 4 Bytes ...
Page 19
... CS SI Opcode SO Each transition represents 8 bits 3597O–DFLASH–10/09 Sector 0 (0a, 0b) (Pages 0-7) Bit 7, 6 details the values read from the Sector Lockdown Register. Sector Lockdown Register xx = Dummy Byte Data Byte AT45DB321D 0 (0a, 0b) See Below 0a 0b (Pages 8-127) Bit 5, 4 Bit ...
Page 20
... Therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued. Figure 10-3. Program Security Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB321D 20 Security Register • • • One-time User Programmable , during which time the Status Register will indicate that the device is busy. If the device P ...
Page 21
... CS pin transitions from a low to a high state. Dur- ing the transfer of a page of data (t monitored to determine whether the transfer has been completed. 3597O–DFLASH–10/ Data Byte n ), the status register can be read or the RDY/BUSY can be XFR AT45DB321D Data Byte Data Byte ...
Page 22
... AT45DB321D 22 ), the status register and the RDY/BUSY pin will indicate that COMP Figure 25-1 (page 46) is recommended ...
Page 23
... The device density is indicated using bits and 2 of the status register. For the AT45DB321D, the four bits are 1101 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
Page 24
... RDPD down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB321D 24 time. Once the device has entered the Deep Power-down mode, all instructions EDPD CS SI Each transition represents 8 bits time before the device can receive any commands ...
Page 25
... Figure 13-1. Erase Sector Protection Register 3597O–DFLASH–10/09 Section , during which time the Status Register will indicate that the device Opcode Opcode SI Byte 1 Byte 2 Each transition represents 8 bits AT45DB321D Section 26. ”Ordering Information” on 13.1). Byte 1 Byte 2 Byte 3 3DH 2AH 80H Opcode Opcode Byte 3 Byte 4 ...
Page 26
... Value Bit 7 Bit 6 Bit 5 Bit 4 00H 14.1.4 Byte 4 – Extended Device Information String Length Byte Count Hex Value Bit 7 Bit 6 Bit 5 Bit 4 00H AT45DB321D 26 Bit 3 Bit 2 Bit 1 Bit Density Code Bit 3 Bit 2 Bit 1 Bit Product Version Code Bit 3 Bit 2 Bit 1 Bit 0 ...
Page 27
... Manufacturer ID Device ID Device ID Extended Byte 1 Byte 2 Byte 3 Device Information String Length AT45DB321D Data Data Extended Extended Device Device Information Information Byte x Byte This information would only be output if the Extended Device Information String Length value was something other than 00H. ...
Page 28
... Buffer 1 to Main Memory Page Program without Built-in Erase Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 AT45DB321D 28 Read Commands Program and Erase Commands Opcode D2H E8H 03H ...
Page 29
... Note: 3597O–DFLASH–10/09 Protection and Security Commands Additional Commands (1) Legacy Commands 1. These legacy commands are not recommended for new designs. AT45DB321D Opcode 3DH + 2AH + 7FH + A9H 3DH + 2AH + 7FH + 9AH 3DH + 2AH + 7FH + CFH 3DH + 2AH + 7FH + FCH 32H 3DH + 2AH + 7FH + 30H ...
Page 30
... B9h ABh D1h D2h D3h D4h D6h D7h E8h Notes Don’t Care AT45DB321D 30 Address Byte Address Byte N/A N/A N/A N/A N/A N N/A N Address Byte ...
Page 31
... E8h Notes Page Address Bit B = Byte/Buffer Address Bit 3597O–DFLASH–10/09 Address Byte Address Byte N/A N/A N/A N/A N/A N N/A N Don’t Care AT45DB321D Address Byte N/A N Additional Don’t Care Bytes B N N/A x N/A x N/A x N/A x N/A ...
Page 32
... The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. AT45DB321D 32 . During power-up, the internal Power-on Reset circuitry keeps the device in ...
Page 33
... Maximum Ratings" are intended to accommo- + 0.6V date short duration undershoot/overshoot condi- CC tions and does not imply or guarantee functional device operation at these levels for any extended period of time AT45DB321D (2.5V Version) -40°C to 85°C 2.5V to 3.6V AT45DB321D AT45DB321D -40° 85° C 2.7V to 3.6V ...
Page 34
... IH V Output Low Voltage OL V Output High Voltage OH Notes during a buffer read maximum @ 20 MHz. CC1 2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guaranteed by design to be 5-Volt tolerant. AT45DB321D 34 Condition Min CS, RESET all IH inputs at CMOS levels CS, RESET all IH inputs at CMOS levels MHz ...
Page 35
... Version) AT45DB321D Min Typ Max Min 6.8 6.8 6.8 6.8 0.1 0.1 0.1 0 100 200 200 100 1.6 5 TBD TBD AT45DB321D Typ Max Units 66 MHz 66 MHz 33 MHz ns ns V/ns V/ 100 µs 1 µs 3 µs 35 µs 200 µs 200 µ 100 ms 1 TBD ...
Page 36
... SPI Mode 0 and SPI Mode 3, respectively. Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These are similar to waveform 1 and waveform 2, except that output SO is not restricted to become valid during the t imum frequency = 66 MHz) of the RapidS serial case. AT45DB321D 36 2.4V AC DRIVING 1 ...
Page 37
... SO SI 3597O–DFLASH–10/ CSS VALID OUT VALID CSS VALID OUT VALID MHz) MAX CSS VALID OUT VALID MHz) MAX CSS VALID OUT VALID IN AT45DB321D CSH t DIS HIGH IMPEDANCE CSH t DIS HIGH IMPEDANCE CSH t DIS HIGH IMPEDANCE CSH t DIS HIGH IMPEDANCE 37 ...
Page 38
... Master clocks out second bit of BYTE-MOSI on the same rising edge of SCK. D. Last bit of BYTE-MOSI is clocked out from the Master. E. Last bit of BYTE-MOSI is clocked into the slave. F. Slave clocks out first bit of BYTE-SO. G. Master clocks in first bit of BYTE-SO. H. Slave clocks out second bit of BYTE-SO. I. Master clocks in last bit of BYTE-SO. AT45DB321D 38 Function ...
Page 39
... HIGH IMPEDANCE CMD 8 bits 8 bits Don’t Care Page Address Bits (A21 - A9) CMD 8 bits 8 bits 8 bits Don’t Care Page Address Bit (PA12 - PA0) AT45DB321D t REC t RST HIGH IMPEDANCE 8 bits LSB Byte/Buffer Address (A8 - A0/BFA8 - BFA0 LSB Byte/Buffer Address (BA9 - BA0/BFA9 - BFA0) t CSS 39 ...
Page 40
... Buffer Write CS SI (INPUT) CMD 22.2 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page (INPUT) Each transition represents 8 bits AT45DB321D 40 FLASH MEMORY ARRAY WRITE I/O INTERFACE SI BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 X BFA7-0 X···X, BFA9-8 ...
Page 41
... I/O INTERFACE SO ADDRESS FOR BINARY PAGE SIZE A15-A8 A21-A16 A7-A0 PA12-6 PA5-0, BA9-8 BA7-0 BINARY PAGE SIZE A21- DON'T CARE BITS CMD PA12-6 AT45DB321D MAIN MEMORY PAGE TO BUFFER 2 BUFFER 2 (512/528 BYTES) BUFFER 2 READ Dummy Bytes n n+1 Starts reading page data into buffer ...
Page 42
... Continuous Array Read (Legacy Opcode E8H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.2 Continuous Array Read (Opcode 0BH SCK OPCODE MSB HIGH-IMPEDANCE SO AT45DB321D 42 BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 CMD X X..X, BFA9-8 BFA7 ADDRESS BITS 32 DON'T CARE BITS MSB MSB ADDRESS BITS A21 - A0 ...
Page 43
... OPCODE ADDRESS BITS A21- MSB ADDRESS BITS 32 DON'T CARE BITS MSB MSB ADDRESS BITS BINARY PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 STANDARD DATAFLASH PAGE SIZE = 14 DON'T CARE + BFA9-BFA0 MSB MSB AT45DB321D DATA BYTE MSB MSB DATA BYTE MSB DON'T CARE DATA BYTE 1 ...
Page 44
... SCK MSB HIGH-IMPEDANCE SO 24.7 Read Sector Protection Register (Opcode 32H SCK MSB HIGH-IMPEDANCE SO 24.8 Read Sector Lockdown Register (Opcode 35H SCK MSB HIGH-IMPEDANCE SO AT45DB321D ADDRESS BITS BINARY PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 STANDARD DATAFLASH PAGE SIZE = OPCODE 14 DON'T CARE + BFA9-BFA0 MSB ...
Page 45
... HIGH-IMPEDANCE SO Note: Each transition 3597O–DFLASH–10/ OPCODE DON'T CARE MSB OPCODE STATUS REGISTER DATA MSB OPCODE 9FH 1FH DEVICE ID BYTE 1 shown for SI and SO represents one byte (8 bits) AT45DB321D DATA BYTE MSB MSB STATUS REGISTER DATA MSB MSB DEVICE ID BYTE 2 00H 45 ...
Page 46
... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB321D 46 START provide address ...
Page 47
... MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) BUFFER WRITE (84H, 87H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) (2) AUTO PAGE REWRITE (58H, 59H) INCREMENT PAGE (2) ADDRESS POINTER END AT45DB321D If planning to modify multiple bytes currently stored within a page of the Flash array 47 ...
Page 48
... Ordering Information 26.1 Ordering Code Detail Atmel Designator Product Family Device Density 32 = 32-megabit Interface 1 = Serial Device Revision AT45DB321D – Device Grade U = Matte Sn lead finish, industrial temperature range (-40°C to +85°C) Package Option M = 8-pad MLF (VDFN 8-pad MLF (VDFN 8-lead, 0.209" wide SOIC ...
Page 49
... AT45DB321D-MWU-SL954 (4) AT45DB321D-MWU-SL955 AT45DB321D-SU (3) AT45DB321D-SU-SL954 (4) AT45DB321D-SU-SL955 AT45DB321D-TU AT45DB321D-CU AT45DB321D-MU-2.5 AT45DB321D-SU-2.5 Notes: 1. The shipping carrier option is not marked on the devices. 2. Standard parts are shipped with the page size set to 528 bytes. The user is able to configure these parts to a 512-byte page size if desired. 3. Parts ordered with suffix SL954 are shipped in bulk with the page size set to 512 bytes. Parts will have a 954 or SL954 marked on them ...
Page 50
... Packaging Information 27.1 8M1-A – MLF (VDFN) Pin TOP VIEW Pin #1 Notch e (0. BOTTOM VIEW Package Drawing Contact: packagedrawings@atmel.com AT45DB321D 0. TITLE 8M1-A, 8-pad 1.00 mm Body, Thermally Enhanced Plastic Very Thin Dual Flat No Lead Package (VDFN) SIDE VIEW A3 A1 0.08 C COMMON DIMENSIONS ...
Page 51
... R 3597O–DFLASH–10/09 1 Option A Pin #1 Chamfer (C 0.30) Option B e Pin #1 K Notch (0.20 R) TITLE 8MW, 8-pad 1.0 mm Body, Very Thin Dual Flat Package No Lead (MLF) AT45DB321D SIDE VIEW A1 A COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM SYMBOL A – – A1 – – b 0.35 ...
Page 52
... Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com AT45DB321D TOP VIEW ...
Page 53
... Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3597O–DFLASH–10/09 PIN SEATING PLANE A1 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) AT45DB321D 0º ~ 5º GAGE PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A – – ...
Page 54
... Ball Grid Array Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 1.00 (0.039) REF 1.00 (0.0394) BSC NON-ACCUMULATIVE 1.00 (0.0394) BSC NON-ACCUMULATIVE 2325 Orchard Parkway San Jose, CA 95131 R AT45DB321D 54 6.10(0.240) 5.90(0.232 8.10(0.319) 7.90(0.311) TOP VIEW 1.40 (0.055) MAX 4.0 (0.157 ...
Page 55
... Changed the Product Version Code to 00001. Corrected typographical errors. Added errata regarding Chip Erase. Added AT45DB321D-SU to ordering information and corresponding 8S2 package. Removed “not recommended for new designs” note from ordering information for 8MW package. Added AT45DB321D-CNU to ordering information and corresponding 8CN3 package. Removed “ ...
Page 56
... Increased typical value from 5 µ µA. - Increased maximum value from 15 µ µA. Updated Absolute Maximum Ratings Added 24C1 24 Ball BGA package Option Deleted DataFlash Card Package Option Added the 2.5V V option CC Removed AT45DB321D-MWU-2.5 and AT45DB321D-TU-2.5 from the Ordering Information table. 3597O–DFLASH–10/09 ...
Page 57
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...