AD6657AEBZ Analog Devices, AD6657AEBZ Datasheet - Page 13

• Manufacturer Part Number: AD6657AEBZ
• Description: Data Conversion IC Development Tools 11 Bit 200 Msps Quad IF Receiver
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD6657Ar

Specifications of AD6657AEBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD6657A
• Interface Type: SPI, USB
• Operating Supply Voltage: 6 V
• Description/function: Quad IF receiver with noise shaping requantizer
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 2 A
• Factory Pack Quantity: 1
• For Use With: HSC-ADC-EVALCZ

Data Sheet
Pin No.
M9
L9
K10
J10
M10
L10
K11
J11
M11
L11
K12
J12
M12
L12
K1
J1
M1
L1
K2
J2
M2
L2
K3
J3
M3
L3
K4
J4
M4
L4
K5
J5
M5
L5
K6
J6
M6
L6
C9
C8
C7
C6
C5
C4
Mnemonic
D5+AB
D5−AB
D6+AB
D6−AB
D7+AB
D7−AB
D8+AB
D8−AB
D9+AB
D9−AB
D10+AB
D10−AB
DCO+AB
DCO−AB
D0+CD
D0−CD
D1+CD
D1−CD
D2+CD
D2−CD
D3+CD
D3−CD
D4+CD
D4−CD
D5+CD
D5−CD
D6+CD
D6−CD
D7+CD
D7−CD
D8+CD
D8−CD
D9+CD
D9−CD
D10+CD
D10−CD
DCO+CD
DCO−CD
MODE
SYNC
PDWN
SCLK
SDIO
CSB
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input/Output
Input
Rev. 0 | Page 13 of 36
Description
Channel A and Channel B LVDS Output Data 5—True.
Channel A and Channel B LVDS Output Data 5—Complement.
Channel A and Channel B LVDS Output Data 6—True.
Channel A and Channel B LVDS Output Data 6—Complement.
Channel A and Channel B LVDS Output Data 7—True.
Channel A and Channel B LVDS Output Data 7—Complement.
Channel A and Channel B LVDS Output Data 8—True.
Channel A and Channel B LVDS Output Data 8—Complement.
Channel A and Channel B LVDS Output Data 9—True.
Channel A and Channel B LVDS Output Data 9—Complement.
Channel A and Channel B LVDS Output Data 10—True.
Channel A and Channel B LVDS Output Data 10—Complement.
Data Clock LVDS Output for Channel A and Channel B—True.
Data Clock LVDS Output for Channel A and Channel B—Complement.
Channel C and Channel D LVDS Output Data 0—True.
Channel C and Channel D LVDS Output Data 0—Complement.
Channel C and Channel D LVDS Output Data 1—True.
Channel C and Channel D LVDS Output Data 1—Complement.
Channel C and Channel D LVDS Output Data 2—True.
Channel C and Channel D LVDS Output Data 2—Complement.
Channel C and Channel D LVDS Output Data 3—True.
Channel C and Channel D LVDS Output Data 3—Complement.
Channel C and Channel D LVDS Output Data 4—True.
Channel C and Channel D LVDS Output Data 4—Complement.
Channel C and Channel D LVDS Output Data 5—True.
Channel C and Channel D LVDS Output Data 5—Complement.
Channel C and Channel D LVDS Output Data 6—True.
Channel C and Channel D LVDS Output Data 6—Complement.
Channel C and Channel D LVDS Output Data 7—True.
Channel C and Channel D LVDS Output Data 7—Complement.
Channel C and Channel D LVDS Output Data 8—True.
Channel C and Channel D LVDS Output Data 8—Complement.
Channel C and Channel D LVDS Output Data 9—True.
Channel C and Channel D LVDS Output Data 9—Complement.
Channel C and Channel D LVDS Output Data 10—True.
Channel C and Channel D LVDS Output Data 10—Complement.
Data Clock LVDS Output for Channel C and Channel D—True.
Data Clock LVDS Output for Channel C and Channel D—Complement.
Mode Select Pin. Logic low enables NSR; logic high disables NSR.
Digital Synchronization Pin.
Power-Down Input (Active High).
SPI Clock.
SPI Data.
SPI Chip Select (Active Low).
AD6657A