AD6657AEBZ Analog Devices, AD6657AEBZ Datasheet - Page 21

• Manufacturer Part Number: AD6657AEBZ
• Description: Data Conversion IC Development Tools 11 Bit 200 Msps Quad IF Receiver
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD6657Ar

Specifications of AD6657AEBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD6657A
• Interface Type: SPI, USB
• Operating Supply Voltage: 6 V
• Description/function: Quad IF receiver with noise shaping requantizer
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 2 A
• Factory Pack Quantity: 1
• For Use With: HSC-ADC-EVALCZ

Data Sheet
For the popular IF band of 140 MHz, Figure 40 shows an
example of a 1:4 transformer passive configuration where a
differential inductor is used to resonate with the internal input
capacitance of the AD6657A. This configuration realizes excellent
noise and distortion performance. Figure 41 shows an example
of an active front-end configuration using the
able gain amplifier (VGA). This configuration is recommended
when signal gain is required.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the
inputs, CLK+ and CLK−, with a differential signal. The signal is
typically ac-coupled into the CLK+ and CLK− pins via a trans-
former or capacitors. These pins are biased internally and require
no external bias (see Figure 42).
Clock Input Options
The
clock input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern (see the Jitter Considerations section).
AD6657A
CLK+
has a very flexible clock input structure. The
Figure 42. Equivalent Clock Input Circuit
2pF
AVDD
1.2V
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
ANALOG
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
AD6657A
Z = 50Ω
AD8376
INPUT
INPUT
0.1µF
Figure 41. Active Front-End Configuration Using the AD8376
AD8376
1µH
1µH
XFMR 1:4 Z
ETC4-1T-7
sample clock
2pF
Figure 40. 1:4 Transformer Passive Configuration
1000pF
1000pF
CLK–
VPOS
1nF
dual vari-
0.1µF
0.1µF
0.1µF
180nH
180nH
301Ω
0.1µF
Rev. 0 | Page 21 of 36
5.1pF
220nH
220nH
121Ω
121Ω
3.9pF
165Ω
165Ω
33Ω
33Ω
Figure 43 and Figure 44 show two preferred methods for clocking
the
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer config-
uration is recommended for clock frequencies from 10 MHz to
200 MHz. The back-to-back Schottky diodes across the trans-
former/balun secondary limit clock excursions into the
to approximately 0.8 V p-p differential. This limit helps to prevent
the large voltage swings of the clock from feeding through to
other portions of the
fall times of the signal that are critical to a low jitter performance.
431nH
15pF
CLOCK
VCM
INPUT
1nF
CLOCK
AD6657A
INPUT
Figure 43. Transformer-Coupled Differential Clock (Up to 200 MHz)
3.0kΩ
Figure 44. Balun-Coupled Differential Clock (Up to 625 MHz)
VCM
68nH
50Ω
0.1µF
3.0kΩ║3.0pF
50Ω
3.0pF
(at clock rates of up to 625 MHz). A low jitter clock
1nF
INTERNAL
AD6657A
1nF
INPUT Z
100Ω
ADC
ADT1-1WT, 1:1Z
AD6657A,
XFMR
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
yet preserves the fast rise and
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
CLK+
CLK–
AD6657A
CLK+
CLK–
ADC
AD6657A
ADC