EVAL-AD7450ASDZ Analog Devices, EVAL-AD7450ASDZ Datasheet - Page 25

• Manufacturer Part Number: EVAL-AD7450ASDZ
• Description: Data Conversion IC Development Tools EVALUATION BOARD I.C.
• Manufacturer: Analog Devices
• Type: ADCr
• Series: AD7450Ar

Specifications of EVAL-AD7450ASDZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD7450A
• Interface Type: Serial
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 1

Thus, the average power dissipated during each cycle with a
throughput rate of 100 kSPS is (2/10) × 4 mW = 0.8 mW.
This is how the power numbers in Figure 44 are calculated.
For throughput rates above 320 kSPS, it is recommended to
reduce the serial clock frequency for best power performance.
MICROPROCESSOR AND DSP INTERFACING
The serial interface on the AD7440/AD7450A allows the parts
to be directly connected to many different microprocessors.
This section explains how to interface the AD7440/AD7450A
with some of the more common microcontroller and DSP serial
interface protocols.
AD7440/AD7450A to ADSP-21xx
The ADSP-21xx family of DSPs is interfaced directly to the
AD7440/AD7450A without any glue logic required.
The SPORT control register should be set up as follows:
Table 7.
Parameter
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
SLEN = 1111
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
To implement power-down mode, SLEN should be set to 1001
to issue an 8-bit SCLK burst.
0.01
100
Figure 44. Power vs. Throughput Rate for Power-Down Mode
0.1
10
1
0
50
100
THROUGHPUT (kSPS)
150
V
DD
Description
Alternate framing
Active low frame signal
Right-justify data
16-bit data-words
Internal serial clock
Frame every word
200
= 5V
V
DD
= 3V
250
300
350
Rev. C | Page 25 of 28
The connection diagram is shown in Figure 45. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to
applications, equidistant sampling is necessary. However in this
example, the timer interrupt is used to control the sampling rate
of the ADC; under certain conditions, equidistant sampling
may not be achieved.
The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and therefore
the reading of data. The frequency of the serial clock is set in
the SCLKDIV register. When the instruction to transmit with
TFS is given (AX0 = TX0), the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
again before starting transmission. If the timer and SCLK values
are chosen such that the instruction to transmit occurs on or
near the rising edge of SCLK, then the data may be transmitted
or it may wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained and eight master clock periods
elapse for every SCLK period. If the timer registers are loaded
with the value 803, then 100.5 SCLKs occur between interrupts
and subsequently between transmit instructions. This situation
results in nonequidistant sampling as the transmit instruction is
occurring on a SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling is
implemented by the DSP.
*ADDITIONAL PINS REMOVED FOR CLARITY
AD7450A*
AD7440/
SDATA
SCLK
CS
Figure 45. Interfacing to the ADSP-21xx
CS and, as with all signal processing
AD7440/AD7450A
SCLK
DR
RFS
TFS
ADSP-21xx*